公开(公告)号：US20140321476A1

公开(公告)日：2014-10-30

申请号：US14254893

申请日：2014-04-17

Applicant: MEDIATEK INC.

Inventor： Yi-Hsin Yu ,  Yu-Hsun Chen ,  Jui-Tse Lin ,  Ta Hsing Liu

IPC: H04L12/875

CPC classification number: H04L47/56 ,  H04L47/6235

Abstract: One packet output controller includes a scheduler and a dequeue device. The scheduler performs a single scheduler operation to schedule an output queue selected from a plurality of output queues associated with an egress port. The dequeue device dequeues multiple packets from the scheduled output queue decided by the single scheduler operation. Another packet output controller includes a scheduler and a dequeue device. The scheduler performs a plurality of scheduler operations each scheduling an output queue selected from a plurality of output queues associated with an egress port. The scheduler performs a current scheduler operation, regardless of a status of a packet transmission of a scheduled output queue decided by a previous scheduler operation. The dequeue device dequeues at least one packet from the scheduled output queue decided by the current scheduler operation after the packet transmission of the scheduled output queue decided by the previous scheduler operation is complete.

Abstract translation: 一个分组输出控制器包括调度器和出队设备。 调度器执行单个调度器操作以调度从与出口端口相关联的多个输出队列中选择的输出队列。 出队设备从由单个调度器操作决定的调度输出队列中排队多个数据包。 另一分组输出控制器包括调度器和出队设备。 调度器执行多个调度器操作，每个调度器操作调度从与出口端口相关联的多个输出队列中选择的输出队列。 调度器执行当前调度器操作，而不管由先前的调度器操作决定的调度输出队列的分组传输的状态。 在由先前的调度器操作确定的调度输出队列的分组传输完成之后，出队设备从由当前调度器操作决定的调度输出队列中的至少一个分组出队。

公开(公告)号：US09634953B2

公开(公告)日：2017-04-25

申请号：US14252722

申请日：2014-04-14

Applicant: MEDIATEK INC.

Inventor： Yi-Hsin Yu ,  Yu-Hsun Chen ,  Chang-Po Ma ,  Jui-Tse Lin ,  Ta Hsing Liu

IPC: H04L12/863

CPC classification number: H04L47/622 ,  H04L47/6235

Abstract: A scheduler performs a plurality of scheduler operations each scheduling an output queue selected from a plurality of output queues associated with an egress port. The scheduler includes a candidate decision logic and a final decision logic. The candidate decision logic is arranged to decide a plurality of candidate output queues for a current scheduler operation, regardless of a resultant status of packet transmission of at least one scheduled output queue decided by at least one previous scheduler operation. The final decision logic is arranged to select one of the candidate output queues as a scheduled output queue decided by the current scheduler operation after obtaining the resultant status of packet transmission of the at least one scheduled output queue decided by the at least one previous scheduler operation.

公开(公告)号：US09667561B2

公开(公告)日：2017-05-30

申请号：US14254893

申请日：2014-04-17

Applicant: MEDIATEK INC.

Inventor： Yi-Hsin Yu ,  Yu-Hsun Chen ,  Jui-Tse Lin ,  Ta Hsing Liu

IPC: H04L12/875 ,  H04L12/863

CPC classification number: H04L47/56 ,  H04L47/6235

Abstract: One packet output controller includes a scheduler and a dequeue device. The scheduler performs a single scheduler operation to schedule an output queue selected from a plurality of output queues associated with an egress port. The dequeue device dequeues multiple packets from the scheduled output queue decided by the single scheduler operation. Another packet output controller includes a scheduler and a dequeue device. The scheduler performs a plurality of scheduler operations each scheduling an output queue selected from a plurality of output queues associated with an egress port. The scheduler performs a current scheduler operation, regardless of a status of a packet transmission of a scheduled output queue decided by a previous scheduler operation. The dequeue device dequeues at least one packet from the scheduled output queue decided by the current scheduler operation after the packet transmission of the scheduled output queue decided by the previous scheduler operation is complete.

公开(公告)号：US20140321475A1

公开(公告)日：2014-10-30

申请号：US14252722

申请日：2014-04-14

Applicant: MEDIATEK INC.

Inventor： Yi-Hsin Yu ,  Yu-Hsun Chen ,  Chang-Po Ma ,  Jui-Tse Lin ,  Ta Hsing Liu

IPC: H04L12/863

CPC classification number: H04L47/622 ,  H04L47/6235

Abstract: A scheduler performs a plurality of scheduler operations each scheduling an output queue selected from a plurality of output queues associated with an egress port. The scheduler includes a candidate decision logic and a final decision logic. The candidate decision logic is arranged to decide a plurality of candidate output queues for a current scheduler operation, regardless of a resultant status of packet transmission of at least one scheduled output queue decided by at least one previous scheduler operation. The final decision logic is arranged to select one of the candidate output queues as a scheduled output queue decided by the current scheduler operation after obtaining the resultant status of packet transmission of the at least one scheduled output queue decided by the at least one previous scheduler operation.

Abstract translation: 调度器执行多个调度器操作，每个调度器操作调度从与出口端口相关联的多个输出队列中选择的输出队列。 调度器包括候选决策逻辑和最终决策逻辑。 候选决策逻辑被布置成为当前调度器操作确定多个候选输出队列，而不管由至少一个先前的调度器操作决定的至少一个调度的输出队列的分组传输的结果状态。 最终决定逻辑被设置为在获得由至少一个先前调度器操作决定的至少一个调度输出队列的分组传输的结果状态之后，选择一个候选输出队列作为由当前调度器操作决定的调度输出队列 。

公开(公告)号：US20140321473A1

公开(公告)日：2014-10-30

申请号：US14230005

申请日：2014-03-31

Applicant: MEDIATEK INC.

Inventor： Yu-Hsun Chen ,  Yi-Hsin Yu ,  Ming-Shi Liou ,  Ming Zhang

IPC: H04L12/861

CPC classification number: H04L49/90 ,  H04L47/39

Abstract: An active output buffer controller is used for controlling a packet data output of a main buffer in a network device. The active output buffer controller has a credit evaluation circuit and a control logic. The credit evaluation circuit estimates a credit value based on at least one of an ingress data reception status of the network device and an egress data transmission status of the network device. The control logic compares the credit value with a first predetermined threshold value to generate a comparison result, and controls the packet data output of the main buffer according to at least the comparison result.

Abstract translation: 主动输出缓冲控制器用于控制网络设备中主缓冲区的分组数据输出。 有源输出缓冲器控制器具有信用评估电路和控制逻辑。 信用评估电路基于网络设备的入口数据接收状态和网络设备的出口数据传输状态中的至少一个来估计信用值。 控制逻辑将信用值与第一预定阈值进行比较以产生比较结果，并且至少根据比较结果来控制主缓冲器的分组数据输出。