公开(公告)号：US20140321476A1

公开(公告)日：2014-10-30

申请号：US14254893

申请日：2014-04-17

Applicant: MEDIATEK INC.

Inventor： Yi-Hsin Yu ,  Yu-Hsun Chen ,  Jui-Tse Lin ,  Ta Hsing Liu

IPC: H04L12/875

CPC classification number: H04L47/56 ,  H04L47/6235

Abstract: One packet output controller includes a scheduler and a dequeue device. The scheduler performs a single scheduler operation to schedule an output queue selected from a plurality of output queues associated with an egress port. The dequeue device dequeues multiple packets from the scheduled output queue decided by the single scheduler operation. Another packet output controller includes a scheduler and a dequeue device. The scheduler performs a plurality of scheduler operations each scheduling an output queue selected from a plurality of output queues associated with an egress port. The scheduler performs a current scheduler operation, regardless of a status of a packet transmission of a scheduled output queue decided by a previous scheduler operation. The dequeue device dequeues at least one packet from the scheduled output queue decided by the current scheduler operation after the packet transmission of the scheduled output queue decided by the previous scheduler operation is complete.

Abstract translation: 一个分组输出控制器包括调度器和出队设备。 调度器执行单个调度器操作以调度从与出口端口相关联的多个输出队列中选择的输出队列。 出队设备从由单个调度器操作决定的调度输出队列中排队多个数据包。 另一分组输出控制器包括调度器和出队设备。 调度器执行多个调度器操作，每个调度器操作调度从与出口端口相关联的多个输出队列中选择的输出队列。 调度器执行当前调度器操作，而不管由先前的调度器操作决定的调度输出队列的分组传输的状态。 在由先前的调度器操作确定的调度输出队列的分组传输完成之后，出队设备从由当前调度器操作决定的调度输出队列中的至少一个分组出队。

公开(公告)号：US09634953B2

公开(公告)日：2017-04-25

申请号：US14252722

申请日：2014-04-14

Applicant: MEDIATEK INC.

Inventor： Yi-Hsin Yu ,  Yu-Hsun Chen ,  Chang-Po Ma ,  Jui-Tse Lin ,  Ta Hsing Liu

IPC: H04L12/863

CPC classification number: H04L47/622 ,  H04L47/6235

Abstract: A scheduler performs a plurality of scheduler operations each scheduling an output queue selected from a plurality of output queues associated with an egress port. The scheduler includes a candidate decision logic and a final decision logic. The candidate decision logic is arranged to decide a plurality of candidate output queues for a current scheduler operation, regardless of a resultant status of packet transmission of at least one scheduled output queue decided by at least one previous scheduler operation. The final decision logic is arranged to select one of the candidate output queues as a scheduled output queue decided by the current scheduler operation after obtaining the resultant status of packet transmission of the at least one scheduled output queue decided by the at least one previous scheduler operation.

公开(公告)号：US20140321474A1

公开(公告)日：2014-10-30

申请号：US14252789

申请日：2014-04-15

Applicant: MEDIATEK INC.

Inventor： Li-Lien Lin ,  Ta Hsing Liu ,  Jui-Tse Lin

IPC: H04L12/883

CPC classification number: H04L49/9015

Abstract: An output queue of a multi-plane network device includes a first processing circuit, a plurality of storage devices and a second processing circuit. The first processing circuit generates packet selection information based on an arrival sequence of a plurality of packets. The storage devices store a plurality of packet linked lists for the output queue. The second processing circuit dequeues a packet from the output queue by selecting a linked list entry from the packet linked lists according to the packet selection information.

Abstract translation: 多平面网络设备的输出队列包括第一处理电路，多个存储设备和第二处理电路。 第一处理电路基于多个分组的到达顺序来生成分组选择信息。 存储设备存储用于输出队列的多个分组链表。 第二处理电路根据分组选择信息从分组链表中选择一个链表，从输出队列中排队一个分组。

公开(公告)号：US09313148B2

公开(公告)日：2016-04-12

申请号：US14252789

申请日：2014-04-15

Applicant: MEDIATEK INC.

Inventor： Li-Lien Lin ,  Ta Hsing Liu ,  Jui-Tse Lin

IPC: H04L12/26 ,  H04L12/28 ,  H04L12/66 ,  H04L12/883

CPC classification number: H04L49/9015

Abstract: An output queue of a multi-plane network device includes a first processing circuit, a plurality of storage devices and a second processing circuit. The first processing circuit generates packet selection information based on an arrival sequence of a plurality of packets. The storage devices store a plurality of packet linked lists for the output queue. The second processing circuit dequeues a packet from the output queue by selecting a linked list entry from the packet linked lists according to the packet selection information.

Abstract translation: 多平面网络设备的输出队列包括第一处理电路，多个存储设备和第二处理电路。 第一处理电路基于多个分组的到达顺序来生成分组选择信息。 存储设备存储用于输出队列的多个分组链表。 第二处理电路根据分组选择信息从分组链表中选择一个链表，从输出队列中排队一个分组。

公开(公告)号：US20140321471A1

公开(公告)日：2014-10-30

申请号：US14203543

申请日：2014-03-10

Applicant: MEDIATEK INC.

Inventor： Veng-Chong Lau ,  Jui-Tse Lin ,  Li-Lien Lin ,  Chien-Hsiung Chang

IPC: H04L12/947

CPC classification number: H04L49/103 ,  H04L49/3027 ,  H04L49/9094

Abstract: A switching fabric of a network device has a load dispatcher, a plurality of store units, a storage device, a plurality of fetch units, and a load assembler. Each of the store units is used to perform a write operation upon the storage device. Each of the fetch units is used to perform a read operation upon the storage device. The load dispatcher is used to dispatch ingress traffic to the store units, wherein a data rate between the load dispatcher and each of the store units is lower than a data rate of the ingress traffic. The load assembler is used to collect outputs of the fetch units to generate egress traffic, wherein a data rate between the load assembler and each of the fetch units is lower than a data rate of the egress traffic.

Abstract translation: 网络设备的交换结构具有负载分配器，多个存储单元，存储设备，多个提取单元和负载组装器。 每个存储单元用于对存储装置执行写入操作。 每个提取单元用于对存储设备执行读取操作。 负载分派器用于向存储单元分配入口流量，其中负载分派器和每个存储单元之间的数据速率低于入口业务的数据速率。 负载汇编器用于收集提取单元的输出以产生出口流量，其中加载汇编器和每个提取单元之间的数据速率低于出口业务的数据速率。

公开(公告)号：US09667561B2

公开(公告)日：2017-05-30

申请号：US14254893

申请日：2014-04-17

Applicant: MEDIATEK INC.

Inventor： Yi-Hsin Yu ,  Yu-Hsun Chen ,  Jui-Tse Lin ,  Ta Hsing Liu

IPC: H04L12/875 ,  H04L12/863

CPC classification number: H04L47/56 ,  H04L47/6235

Abstract: One packet output controller includes a scheduler and a dequeue device. The scheduler performs a single scheduler operation to schedule an output queue selected from a plurality of output queues associated with an egress port. The dequeue device dequeues multiple packets from the scheduled output queue decided by the single scheduler operation. Another packet output controller includes a scheduler and a dequeue device. The scheduler performs a plurality of scheduler operations each scheduling an output queue selected from a plurality of output queues associated with an egress port. The scheduler performs a current scheduler operation, regardless of a status of a packet transmission of a scheduled output queue decided by a previous scheduler operation. The dequeue device dequeues at least one packet from the scheduled output queue decided by the current scheduler operation after the packet transmission of the scheduled output queue decided by the previous scheduler operation is complete.

公开(公告)号：US20140321475A1

公开(公告)日：2014-10-30

申请号：US14252722

申请日：2014-04-14

Applicant: MEDIATEK INC.

Inventor： Yi-Hsin Yu ,  Yu-Hsun Chen ,  Chang-Po Ma ,  Jui-Tse Lin ,  Ta Hsing Liu

IPC: H04L12/863

CPC classification number: H04L47/622 ,  H04L47/6235

Abstract: A scheduler performs a plurality of scheduler operations each scheduling an output queue selected from a plurality of output queues associated with an egress port. The scheduler includes a candidate decision logic and a final decision logic. The candidate decision logic is arranged to decide a plurality of candidate output queues for a current scheduler operation, regardless of a resultant status of packet transmission of at least one scheduled output queue decided by at least one previous scheduler operation. The final decision logic is arranged to select one of the candidate output queues as a scheduled output queue decided by the current scheduler operation after obtaining the resultant status of packet transmission of the at least one scheduled output queue decided by the at least one previous scheduler operation.

Abstract translation: 调度器执行多个调度器操作，每个调度器操作调度从与出口端口相关联的多个输出队列中选择的输出队列。 调度器包括候选决策逻辑和最终决策逻辑。 候选决策逻辑被布置成为当前调度器操作确定多个候选输出队列，而不管由至少一个先前的调度器操作决定的至少一个调度的输出队列的分组传输的结果状态。 最终决定逻辑被设置为在获得由至少一个先前调度器操作决定的至少一个调度输出队列的分组传输的结果状态之后，选择一个候选输出队列作为由当前调度器操作决定的调度输出队列 。