公开(公告)号：US20130285943A1

公开(公告)日：2013-10-31

申请号：US13748593

申请日：2013-01-24

Applicant: MEDIATEK INC.

Inventor： Chung-Jen Kuo ,  Yu-Hsuan Lin ,  Chang-Po Ma

IPC: G06F3/041

CPC classification number: G06F3/0412 ,  G06F3/041 ,  G06F8/654

Abstract: An exemplary touch controller chip includes a volatile storage device, an interface unit and a control unit. The interface unit is arranged for receiving touch controller firmware outside the touch controller chip, and storing the received touch controller firmware into the volatile storage device. The control unit is arranged for executing the touch controller firmware stored in the volatile storage device to control a touch panel. In addition, an exemplary electronic device includes a touch controller chip and a host, wherein the touch controller chip has no non-volatile storage device used for storing touch controller firmware, and the host is arranged for transmitting the touch controller firmware to the touch controller chip.

Abstract translation: 示例性触摸控制器芯片包括易失性存储设备，接口单元和控制单元。 接口单元被布置成用于在触摸控制器芯片之外接收触摸控制器固件，并将接收到的触摸控制器固件存储到易失性存储设备中。 控制单元被配置为执行存储在易失性存储装置中的触摸控制器固件来控制触摸面板。 此外，示例性电子设备包括触摸控制器芯片和主机，其中触摸控制器芯片没有用于存储触摸控制器固件的非易失性存储设备，并且主机被布置为将触摸控制器固件发送到触摸控制器 芯片。

公开(公告)号：US20140321466A1

公开(公告)日：2014-10-30

申请号：US14197176

申请日：2014-03-04

Applicant: MEDIATEK INC.

Inventor： Chang-Po Ma

IPC: H04L12/741

CPC classification number: H04L45/745

Abstract: A packet processing method includes at least the following steps: deriving a start address from a packet index of a packet to be processed; deriving link-list access control information corresponding to the packet to be processed; and reading packet information for the packet to be processed from a link list stored in a packet information table according to the start address and the link-list access control information, wherein the link list comprises a plurality of entries each indexed by a current address and storing a next address and one packet information.

Abstract translation: 分组处理方法至少包括以下步骤：从要处理的分组的分组索引得出起始地址; 导出与要处理的分组相对应的链路列表访问控制信息; 以及根据起始地址和链接列表访问控制信息从存储在分组信息表中的链接列表读取要处理的分组的分组信息，其中链接列表包括多个条目，每个条目由当前地址索引， 存储下一个地址和一个分组信息。

公开(公告)号：US09634953B2

公开(公告)日：2017-04-25

申请号：US14252722

申请日：2014-04-14

Applicant: MEDIATEK INC.

Inventor： Yi-Hsin Yu ,  Yu-Hsun Chen ,  Chang-Po Ma ,  Jui-Tse Lin ,  Ta Hsing Liu

IPC: H04L12/863

CPC classification number: H04L47/622 ,  H04L47/6235

Abstract: A scheduler performs a plurality of scheduler operations each scheduling an output queue selected from a plurality of output queues associated with an egress port. The scheduler includes a candidate decision logic and a final decision logic. The candidate decision logic is arranged to decide a plurality of candidate output queues for a current scheduler operation, regardless of a resultant status of packet transmission of at least one scheduled output queue decided by at least one previous scheduler operation. The final decision logic is arranged to select one of the candidate output queues as a scheduled output queue decided by the current scheduler operation after obtaining the resultant status of packet transmission of the at least one scheduled output queue decided by the at least one previous scheduler operation.

公开(公告)号：US20140321475A1

公开(公告)日：2014-10-30

申请号：US14252722

申请日：2014-04-14

Applicant: MEDIATEK INC.

Inventor： Yi-Hsin Yu ,  Yu-Hsun Chen ,  Chang-Po Ma ,  Jui-Tse Lin ,  Ta Hsing Liu

IPC: H04L12/863

CPC classification number: H04L47/622 ,  H04L47/6235

Abstract: A scheduler performs a plurality of scheduler operations each scheduling an output queue selected from a plurality of output queues associated with an egress port. The scheduler includes a candidate decision logic and a final decision logic. The candidate decision logic is arranged to decide a plurality of candidate output queues for a current scheduler operation, regardless of a resultant status of packet transmission of at least one scheduled output queue decided by at least one previous scheduler operation. The final decision logic is arranged to select one of the candidate output queues as a scheduled output queue decided by the current scheduler operation after obtaining the resultant status of packet transmission of the at least one scheduled output queue decided by the at least one previous scheduler operation.

Abstract translation: 调度器执行多个调度器操作，每个调度器操作调度从与出口端口相关联的多个输出队列中选择的输出队列。 调度器包括候选决策逻辑和最终决策逻辑。 候选决策逻辑被布置成为当前调度器操作确定多个候选输出队列，而不管由至少一个先前的调度器操作决定的至少一个调度的输出队列的分组传输的结果状态。 最终决定逻辑被设置为在获得由至少一个先前调度器操作决定的至少一个调度输出队列的分组传输的结果状态之后，选择一个候选输出队列作为由当前调度器操作决定的调度输出队列 。

公开(公告)号：US20170153852A1

公开(公告)日：2017-06-01

申请号：US15331912

申请日：2016-10-23

Applicant: MEDIATEK INC.

Inventor： Chang-Po Ma ,  Veng-Chong Lau ,  Ting-Chun Chang ,  Yao-Chun Fang ,  Pi-Hai Liu ,  Li-Lien Lin

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0679 ,  H04L49/90

Abstract: A packet buffer stores packet data of packets received by a master device. The packet buffer includes a non-guaranteed buffer, a guaranteed buffer, and a reserved buffer. The non-guaranteed buffer is visible to the master device, and is not guaranteed to provide one free cell space for one cell in a first-type packet before the non-guaranteed buffer is full. The guaranteed buffer is visible to the master device, and is guaranteed to provide one free cell space for one cell in a second-type packet before the guaranteed buffer is full. The reserved buffer is invisible to the master device, and is arranged to provide headroom for the guaranteed buffer.