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公开(公告)号：US20160164546A1
公开(公告)日：2016-06-09
申请号：US15044079
申请日：2016-02-15
Applicant: MEDIATEK INC.
Inventor： Saravanan Rajapandian , Caiyi Wang , Jing Li , Ravikanth Suravarapu , Narayanan Baskaran
CPC classification number: H04B1/005 , H03G3/3036 , H04B1/18
Abstract: A current buffer used in a receiver arrangement includes a direct path mode and a mirror path mode. The direct path mode includes a plurality of first set of transistors and a plurality of first set of current sources turned on while all remaining transistors and current sources are turned off , during the direct path mode a current signal at an input node directly appears at an output node. The mirror path mode includes a first transistor and a first current source being turned off while a plurality of second set of transistors and a plurality of second set of current sources are turned on. The current signal goes through a current mirror pair and appears at the output node with a gain which is controlled by slicing one of transistors of the current mirror pair and a second current source allowing multiple gains in the mirror path mode.
Abstract translation: 在接收器装置中使用的当前缓冲器包括直接路径模式和镜像路径模式。 直接路径模式包括多个第一组晶体管，并且多个第一组电流源导通，而所有剩余的晶体管和电流源都截止，在直接路径模式期间，输入节点处的电流信号直接出现在 输出节点。 镜路径模式包括第一晶体管和第一电流源被截止，而多个第二组晶体管和多个第二组电流源被接通。 电流信号通过电流镜对并出现在输出节点处，其增益通过对当前镜像对的晶体管中的一个晶体管进行切割和在镜像路径模式中允许多个增益的第二电流源进行控制。
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公开(公告)号：US09407296B2
公开(公告)日：2016-08-02
申请号：US15044079
申请日：2016-02-15
Applicant: MEDIATEK INC.
Inventor： Saravanan Rajapandian , Caiyi Wang , Jing Li , Ravikanth Suravarapu , Narayanan Baskaran
CPC classification number: H04B1/005 , H03G3/3036 , H04B1/18
Abstract: A current buffer used in a receiver arrangement includes a direct path mode and a mirror path mode. The direct path mode includes a plurality of first set of transistors and a plurality of first set of current sources turned on while all remaining transistors and current sources are turned off, during the direct path mode a current signal at an input node directly appears at an output node. The mirror path mode includes a first transistor and a first current source being turned off while a plurality of second set of transistors and a plurality of second set of current sources are turned on. The current signal goes through a current mirror pair and appears at the output node with a gain which is controlled by slicing one of transistors of the current mirror pair and a second current source allowing multiple gains in the mirror path mode.
Abstract translation: 在接收器装置中使用的当前缓冲器包括直接路径模式和镜像路径模式。 直接路径模式包括多个第一组晶体管，并且多个第一组电流源导通，而所有剩余的晶体管和电流源都截止，在直接路径模式期间，输入节点处的电流信号直接出现在 输出节点。 镜路径模式包括第一晶体管和第一电流源被截止，而多个第二组晶体管和多个第二组电流源被接通。 电流信号通过电流镜对并出现在输出节点处，其增益通过对当前镜像对的晶体管中的一个晶体管进行切割和在镜像路径模式中允许多个增益的第二电流源进行控制。
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公开(公告)号：US09300264B2
公开(公告)日：2016-03-29
申请号：US14465841
申请日：2014-08-22
Applicant: MEDIATEK INC.
Inventor： Ravikanth Suravarapu , Saravanan Rajapandian , Narayanan Baskaran , Caiyi Wang , Jing Li
CPC classification number: H04B1/005 , H03G3/3036 , H04B1/18
Abstract: A receiver includes LNA-mixer arrangement, a current buffer arrangement and an analog filter arrangement. The LNA-mixer arrangement receives a plurality of input signals and provides a wide-band input match for a specified frequency range of operation. The LNA-mixer arrangement includes a plurality of LNA structures and a plurality of mixer structures where each of the LNA structure path is coupled to a single mixer structure. The LNA-mixer arrangement outputs a first signal. The current buffer arrangement receives the first signal and reduces the Image Rejection (IR) asymmetry between the high frequency portion and the low frequency portion of the first signal as well as provides a gain to the first signal. The current buffer arrangement outputs a second signal. The analog filter arrangement receives the second signals and perform filtering and calibration.
Abstract translation: 接收机包括LNA混频器布置，当前缓冲器布置和模拟滤波器布置。 LNA混频器装置接收多个输入信号，并在指定的频率操作范围内提供宽带输入匹配。 LNA混合器装置包括多个LNA结构和多个混合器结构，其中每个LNA结构路径耦合到单个混合器结构。 LNA混频器布置输出第一信号。 当前的缓冲器装置接收第一信号并且降低第一信号的高频部分和低频部分之间的图像抑制（IR）不对称性，并且为第一信号提供增益。 当前的缓冲装置输出第二信号。 模拟滤波器装置接收第二信号并执行滤波和校准。
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公开(公告)号：US20160056784A1
公开(公告)日：2016-02-25
申请号：US14465841
申请日：2014-08-22
Applicant: MEDIATEK INC.
Inventor： Saravanan Rajapandian , Caiyi Wang , Jing Li , Ravikanth Suravarapu , Narayanan Baskaran
IPC: H03G3/30
CPC classification number: H04B1/005 , H03G3/3036 , H04B1/18
Abstract: A receiver includes LNA-mixer arrangement, a current buffer arrangement and an analog filter arrangement. The LNA-mixer arrangement receives a plurality of input signals and provides a wide-band input match for a specified frequency range of operation. The LNA-mixer arrangement includes a plurality of LNA structures and a plurality of mixer structures where each of the LNA structure path is coupled to a single mixer structure. The LNA-mixer arrangement outputs a first signal. The current buffer arrangement receives the first signal and reduces the Image Rejection (IR) asymmetry between the high frequency portion and the low frequency portion of the first signal as well as provides a gain to the first signal. The current buffer arrangement outputs a second signal. The analog filter arrangement receives the second signals and perform filtering and calibration.
Abstract translation: 接收机包括LNA混频器布置，当前缓冲器布置和模拟滤波器布置。 LNA混频器装置接收多个输入信号，并在指定的频率操作范围内提供宽带输入匹配。 LNA混合器装置包括多个LNA结构和多个混合器结构，其中每个LNA结构路径耦合到单个混合器结构。 LNA混频器布置输出第一信号。 当前的缓冲器装置接收第一信号并且降低第一信号的高频部分和低频部分之间的图像抑制（IR）不对称性，并且为第一信号提供增益。 当前的缓冲装置输出第二信号。 模拟滤波器装置接收第二信号并执行滤波和校准。
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