公开(公告)号：US20160005208A1

公开(公告)日：2016-01-07

申请号：US14642763

申请日：2015-03-10

Applicant: Mediatek Inc.

Inventor： Ming-Hao Liao ,  Tsung-Liang Hou ,  Chin-Yuan Yao ,  Hung-Wei Wu

IPC: G06T15/00 ,  G06T15/80 ,  G06T15/40

CPC classification number: G06T15/005 ,  G06T15/405

Abstract: A depth processing apparatus includes a depth buffer, an early depth processing circuit, a post depth processing circuit, and a depth processing controller. The depth buffer stores depth information of a plurality of pixels of a screen space. The early depth processing circuit performs early depth processing based on at least a portion of the depth information before a pixel shading stage. The post depth processing circuit performs post depth processing based on at least a portion of the depth information after the pixel shading stage. The depth processing controller manages a plurality of dependency indication values corresponding to a plurality of sub-regions in the screen space, respectively, and configured to control a first pixel for undergoing at least one of the early depth processing and the post depth processing by referring a first dependency indication value of a first sub-region in which the first pixel is located.

Abstract translation: 深度处理装置包括深度缓冲器，早期深度处理电路，后深度处理电路和深度处理控制器。 深度缓冲器存储屏幕空间的多个像素的深度信息。 早期深度处理电路基于像素着色阶段之前的深度信息的至少一部分来执行早期深度处理。 后深度处理电路基于像素着色阶段之后的深度信息的至少一部分来执行后深度处理。 深度处理控制器分别管理与屏幕空间中的多个子区域相对应的多个相关性指示值，并且被配置为控制用于通过参考来进行早期深度处理和后深度处理中的至少一个的第一像素 第一像素所在的第一子区域的第一依赖性指示值。

公开(公告)号：US20150332495A1

公开(公告)日：2015-11-19

申请号：US14675759

申请日：2015-04-01

Applicant: MEDIATEK INC.

Inventor： Ming-Hao Liao ,  Sung-Fang Tsai ,  Pei-Kuei Tsung ,  Hung-Wei Wu

IPC: G06T15/00

CPC classification number: G06T15/005 ,  G06T11/40

Abstract: A graphics processing method and an associated graphics processing apparatus are provided, where the graphics processing method is applied to the graphics processing apparatus, the graphics processing apparatus may be positioned within an electronic device, and the graphics processing apparatus may comprise at least one portion of the electronic device. The graphics processing method includes the steps of: calculating vertex positions of a primitive in a binning phase; determining, according to specific information, whether to compute vertex varyings of the primitive in the binning phase or in a rendering phase so as to provide a determination result; computing the vertex varyings in the binning phase or in the rendering phase according to the determination result; and rendering the primitive according to the vertex positions and the vertex varyings in the rendering phase.

Abstract translation: 提供了图形处理方法和相关联的图形处理装置，其中将图形处理方法应用于图形处理装置，图形处理装置可以位于电子装置内，并且图形处理装置可以包括至少一部分 电子设备。 图形处理方法包括以下步骤：计算合并阶段中原语的顶点位置; 根据具体信息确定是否计算合并阶段或渲染阶段中的原语的顶点变化，以便提供确定结果; 根据确定结果计算合并阶段或渲染阶段中的顶点变化; 并根据渲染阶段中的顶点位置和顶点变化渲染图元。

公开(公告)号：US09846959B2

公开(公告)日：2017-12-19

申请号：US14642763

申请日：2015-03-10

Applicant: MEDIATEK INC.

Inventor： Ming-Hao Liao ,  Tsung-Liang Hou ,  Chin-Yuan Yao ,  Hung-Wei Wu

IPC: G06T15/40 ,  G06T15/00

CPC classification number: G06T15/005 ,  G06T15/405

Abstract: A depth processing apparatus includes a depth buffer, an early depth processing circuit, a post depth processing circuit, and a depth processing controller. The depth buffer stores depth information of a plurality of pixels of a screen space. The early depth processing circuit performs early depth processing based on at least a portion of the depth information before a pixel shading stage. The post depth processing circuit performs post depth processing based on at least a portion of the depth information after the pixel shading stage. The depth processing controller manages a plurality of dependency indication values corresponding to a plurality of sub-regions in the screen space, respectively, and configured to control a first pixel for undergoing at least one of the early depth processing and the post depth processing by referring a first dependency indication value of a first sub-region in which the first pixel is located.

公开(公告)号：US09760969B2

公开(公告)日：2017-09-12

申请号：US14641449

申请日：2015-03-09

Applicant: MEDIATEK INC.

Inventor： Ming-Hao Liao ,  Shou-Jen Lai ,  Chia-Hsien Chou ,  Po-Chun Fan ,  Yan-Hong Lu ,  Chih-Chung Cheng ,  Hung-Yau Lin

IPC: G06T1/20

CPC classification number: G06T1/20

Abstract: A graphic processing system and a method of graphic processing are provided. The graphic processing system has a collector, a plurality of slots, a scheduler, an arbiter and at least an arithmetic logic unit (ALU). The collector is configured to group a plurality of workitems into elementary wavefronts. Each of the elementary wavefronts comprises workitems configured to execute the same kernel code. The scheduler is configured to allocate the elementary wavefronts to the slots. Two or more of the elementary wavefronts exist at one slot to form one of a plurality of macro wavefronts. The arbiter is configured to select one of the macro wavefronts. The ALU is configured to execute workitems of at least an elementary wavefront of the selected macro wavefront and output results of execution of the workitems.

公开(公告)号：US09836869B2

公开(公告)日：2017-12-05

申请号：US15075050

申请日：2016-03-18

Applicant: MediaTek Inc.

Inventor： Sung-Fang Tsai ,  Pei-Kuei Tsung ,  Ming-Hao Liao

IPC: G06T15/00 ,  G06T11/40

CPC classification number: G06T15/005 ,  G06T11/40

Abstract: A graphics-processing method and a graphics-processing apparatus are provided. The graphics-processing method includes the steps of computing a vertex position of a vertex in a binning phase to obtain a first position data; generating a first signal according to a first condition, wherein when the first signal corresponds to a first value, the first position data is stored into a memory unit, and when the first signal corresponds to a second value, the vertex position of the vertex in a rendering phase is computed to obtain a second position data; computing a vertex varying of the vertex in the binning phase or the rendering phase; and rendering in the rendering phase according to either the first position data or the second position data.

公开(公告)号：US20160267621A1

公开(公告)日：2016-09-15

申请号：US14641449

申请日：2015-03-09

Applicant: MEDIATEK INC.

Inventor： Ming-Hao Liao ,  Shou-Jen Lai ,  Chia-Hsien Chou ,  Po-Chun Fan ,  Yan-Hong Lu ,  Chih-Chung Cheng ,  Hung-Yau Lin

IPC: G06T1/20

CPC classification number: G06T1/20

Abstract: A graphic processing system and a method of graphic processing are provided. The graphic processing system has a collector, a plurality of slots, a scheduler, an arbiter and at least an arithmetic logic unit (ALU). The collector is configured to group a plurality of workitems into elementary wavefronts. Each of the elementary wavefronts comprises workitems configured to execute the same kernel code. The scheduler is configured to allocate the elementary wavefronts to the slots. Two or more of the elementary wavefronts exist at one slot to form one of a plurality of macro wavefronts. The arbiter is configured to select one of the macro wavefronts. The ALU is configured to execute workitems of at least an elementary wavefront of the selected macro wavefront and output results of execution of the workitems.

Abstract translation: 提供图形处理系统和图形处理方法。 图形处理系统具有收集器，多个时隙，调度器，仲裁器和至少一个算术逻辑单元（ALU）。 收集器被配置为将多个工作项组合成基本波阵面。 每个基本波前都包括配置为执行相同内核代码的工作项。 调度器被配置为将基本波前分配给时隙。 在一个时隙上存在两个以上的基本波前，形成多个宏波前的一个。 仲裁器被配置为选择一个宏波阵面。 ALU被配置为执行至少所选宏波阵面的基本波阵面的工作项，并输出工作项目的执行结果。

公开(公告)号：US09830731B2

公开(公告)日：2017-11-28

申请号：US15075041

申请日：2016-03-18

Applicant: MediaTek Inc.

Inventor： Pei-Kuei Tsung ,  Sung-Fang Tsai ,  Ming-Hao Liao ,  Yang-Yao Lin ,  Ken-Fu Liang ,  Chun-Shen Liu

IPC: G06T15/00 ,  G06T11/40 ,  G06F9/50

CPC classification number: G06T15/005 ,  G06F9/50 ,  G06T11/40

Abstract: A method of a graphics-processing unit (GPU) for tile-based rendering of a display area and a graphics-processing apparatus are provided. The method includes the steps of computing vertex positions of a plurality of vertexes, wherein the first vertex corresponds to a first thread and the second vertex corresponds to a second thread; determining whether a thread merge condition is satisfied; merging the first thread and the second thread to a thread group when determining that the thread merge condition is satisfied; computing vertex varyings of the plurality of vertexes, wherein when the first thread and the second thread are merged to the thread group, a varying of the first vertex and a varying of the second vertex are computed with respect to a program counter.

公开(公告)号：US09754402B2

公开(公告)日：2017-09-05

申请号：US14675759

申请日：2015-04-01

Applicant: MEDIATEK INC.

Inventor： Ming-Hao Liao ,  Sung-Fang Tsai ,  Pei-Kuei Tsung ,  Hung-Wei Wu

IPC: G06T15/00 ,  G06T11/40

CPC classification number: G06T15/005 ,  G06T11/40

Abstract: A graphics processing method and an associated graphics processing apparatus, where the graphics processing method is applied to the graphics processing apparatus, the graphics processing apparatus may be positioned within an electronic device, and the graphics processing apparatus may comprise at least one portion of the electronic device. The graphics processing method includes the steps of: calculating vertex positions of a primitive in a binning phase; determining, according to specific information, whether to compute vertex varyings of the primitive in the binning phase or in a rendering phase so as to provide a determination result; computing the vertex varyings in the binning phase or in the rendering phase according to the determination result; and rendering the primitive according to the vertex positions and the vertex varyings in the rendering phase.

公开(公告)号：US20160180579A1

公开(公告)日：2016-06-23

申请号：US14576036

申请日：2014-12-18

Applicant: MediaTek Inc.

Inventor： Ming-Hao Liao ,  Chih-Ching Chen ,  Hung-Wei Wu

IPC: G06T15/40 ,  G06T1/20

CPC classification number: G06T15/405 ,  G06T15/005

Abstract: A depth processing method and associated graphic processing circuit is provided. The method comprises loading geometry data of a scene and performing a vertex transformation thereof. After the geometry data is segmented in a tile resolution, pre-depth data of the scene are obtained. After the geometry data are segmented in a bin resolution, plural bin tables are generated. Then, the plural bin tables are converted into plural tiles, the plural converted tiles are classified into a first portion of tiles and a second portion of tiles according to depth data of the converted tiles and the pre-depth data of the scene, and the second portion of tiles are discarded. After the first portion of tiles are processed, a color value and a depth value of each pixel of the scene are generated.

Abstract translation: 提供深度处理方法和相关的图形处理电路。 该方法包括加载场景的几何数据并执行其顶点变换。 在以瓦片分辨率分割几何数据之后，获得场景的深度数据。 在以数据分辨率分割几何数据之后，生成多个表格。 然后，将多个bin表转换成多个瓦片，根据转换瓦片的深度数据和场景的深度数据将多个转换瓦片分类为瓦片的第一部分和瓦片的第二部分，并且 瓦片的第二部分被丢弃。 在对瓷砖的第一部分进行处理之后，生成场景的每个像素的颜色值和深度值。

公开(公告)号：US20160180539A1

公开(公告)日：2016-06-23

申请号：US14582134

申请日：2014-12-23

Applicant: MediaTek Inc.

Inventor： Ming-Hao Liao ,  Chih-Ching Chen ,  Shih-Chin Lin ,  Hung-Wei Wu

IPC: G06T7/00 ,  G06T15/80 ,  G06T15/00 ,  G06T7/40 ,  G06T1/20

CPC classification number: G06T15/005 ,  G06T15/40

Abstract: A graphic processing circuit with binning rendering and associated pre-depth processing method is provided. Firstly, a first depth data of a first primitive corresponding to a specified tile is received. Then, the pre-depth data corresponding to the specified tile is read from a pre-Z buffer. If the first depth data is not larger than the pre-depth data and the first primitive is an opaque primitive, the pre-depth data is updated with the first depth data. If the first depth data is not larger than the pre-depth data and the first primitive is a translucent primitive, an uncertainty ordering range is defined according to the first depth data and the pre-depth data, and the pre-depth data is updated with the uncertainty ordering range.

Abstract translation: 提供了具有binning渲染和相关的预深度处理方法的图形处理电路。 首先，接收对应于指定瓦片的第一原语的第一深度数据。 然后，从预Z缓冲器读取对应于指定瓦片的预深度数据。 如果第一深度数据不大于预深度数据，并且第一原语是不透明原语，则用第一深度数据更新预深度数据。 如果第一深度数据不大于预深度数据，并且第一图元是半透明图元，则根据第一深度数据和预深度数据来定义不确定性排序范围，并且更新预深度数据 具有不确定性排序范围。