-
公开(公告)号：US20100156472A1
公开(公告)日：2010-06-24
申请号：US12645475
申请日：2009-12-22
申请人： Leopold E. Pellon
发明人： Leopold E. Pellon
IPC分类号： H03B21/00
CPC分类号： H03M1/662 , H04B1/0007 , H04B1/40
摘要： A representative integrated circuit comprises a clock signal generator that generates a clock signal, a code pattern generator that generates digital pattern data based on the clock signal, and a transversal digital-to-analog conversion (T-DAC) unit that includes a plurality of registers and a unary modulator (Umod) array. The T-DAC unit provides frequency selection ranges covering wide operational bands based on the digital pattern data and the clock signal.
摘要翻译： 代表性的集成电路包括产生时钟信号的时钟信号发生器，基于时钟信号产生数字图形数据的代码图形发生器和包括多个数字模拟转换（T-DAC）单元的横向数模转换（T-DAC）单元 寄存器和一元调制器（Umod）阵列。 T-DAC单元提供基于数字图形数据和时钟信号覆盖广泛运行频段的频率选择范围。
-
2.发明授权公开(公告)号：US07504976B1
公开(公告)日：2009-03-17
申请号：US11700382
申请日：2007-01-31
申请人： Leopold E. Pellon
发明人： Leopold E. Pellon
IPC分类号： H03M3/00
CPC分类号： H04L27/36 , H03M1/1061 , H03M1/747 , H03M3/41 , H03M3/504 , H03M7/3026 , H03M7/3042
摘要： An RF signal source receives wideband digital signals representing the instantaneous amplitude of the desired RF, and ΣΔ converts to ternary ΣΔ signals. The ternary ΣΔ signals are delayed in a transversal filter and the delayed signals are converted to currents for application to a traveling-wave summer for producing the desired RF. The traveling-wave summer may be a transmission line. The currents may be weighted with a filter response in order to limit the bandwidth of the RF signals. The RF may be coupled out through an antialiasing filter. The digital clocks may be delayed to correspond with the delays of the combiner, to impart directionality to the summed signals.
摘要翻译： RF信号源接收表示所需RF的瞬时幅度的宽带数字信号，并且SigmaDelta转换为三进制SigmaDelta信号。 三元SigmaDelta信号在横向滤波器中被延迟，并且延迟的信号被转换为电流以用于产生所需RF的行波夏季。 行波夏天可能是传输线。 可以用滤波器响应来加权电流，以便限制RF信号的带宽。 RF可以通过抗混叠滤波器耦合出来。 数字时钟可以被延迟以与组合器的延迟相对应，以对求和的信号赋予方向性。
-
公开(公告)号：US08502610B2
公开(公告)日：2013-08-06
申请号：US12645474
申请日：2009-12-22
IPC分类号： H03K3/03
摘要： A representative integrated circuit comprises a clock signal generator that generates a clock signal, a code pattern generator that generates digital pattern data based on the clock signal, and multiple traversal local oscillator synthesizers that are coupled in a cascaded configuration. Each traversal local oscillator synthesizer includes a transversal digital-to-analog conversion (T-DAC) unit that includes a plurality of registers and a unary modulator (Umod) array. The T-DAC provides frequency selection ranges covering wide operational bands based on the digital pattern data and the clock signal.
摘要翻译： 代表性的集成电路包括产生时钟信号的时钟信号发生器，基于时钟信号产生数字图形数据的代码图形发生器和以级联配置耦合的多个遍历本地振荡器合成器。 每个遍历本地振荡器合成器包括包括多个寄存器和一元调制器（Umod）阵列的横向数模转换（T-DAC）单元。 T-DAC提供基于数字图形数据和时钟信号覆盖宽范围操作频段的频率选择范围。
-
公开(公告)号：US07075468B1
公开(公告)日：2006-07-11
申请号：US10963323
申请日：2004-10-12
申请人： Leopold E. Pellon
发明人： Leopold E. Pellon
IPC分类号： H03M3/00
摘要： A Σ) analog-to-digital converter (ADC) includes an ADC converter element which receives resonated signals for generating output digital signals, and also a DAC for generating a reconstituted analog signal therefrom. A summer sums the reconstituted and input analog signals with filtered signals to generate resonated signals for the ADC element. A resonator includes a filter receiving the resonated signals, for producing the filtered signals for application to the summer. The summing circuit, the ADC element, and the digital-to-analog converter are in a first feedback loop, and the summer and the filter are in a second loop. The only coupling between the loops is the summing circuit. The delays of the loops become isolated from each other, and the overall performance of the sigma-delta ADC is dependent only on the longer of the two individual delays, rather than on the sum of the delays. This provides wider bandwidth A-D conversion (150).
摘要翻译： Aigma）模数转换器（ADC）包括ADC转换器元件，其接收用于产生输出数字信号的谐振信号，以及用于从其产生重构的模拟信号的DAC。 一个夏天把重构和输入的模拟信号与滤波信号相加，以产生ADC元件的谐振信号。 谐振器包括接收谐振信号的滤波器，用于产生用于夏季应用的滤波信号。 加法电路，ADC元件和数模转换器处于第一反馈回路中，并且加法器和滤波器处于第二回路中。 环路之间的唯一耦合是求和电路。 环路的延迟彼此隔离，并且Σ-ΔADC的整体性能仅取决于两个单独延迟中的较长时间，而不是延迟的总和。 这提供了更宽带宽的A-D转换（150）。
-
5.发明授权
公开(公告)号：US5392042A
公开(公告)日：1995-02-21
申请号：US102362
申请日：1993-08-05
申请人： Leopold E. Pellon
发明人： Leopold E. Pellon
摘要： A sigma-delta (.SIGMA..DELTA.) analog-to-digital converter (ADC) accepts band-limited analog signals, and subtracts an analog replica of an output pulse- or amplitude-density modulated (ADM) signal therefrom to produce an error signal. The error signal is processed by an analog filter or resonator with a nondelayed forward path and a tapped nonaccumulating delay line, and summed feedback and feedforward weights coupled to the taps, to thereby produce a resonated signal. An ADC processes the resonated signal, and produces the ADM signal. The ADC undesirably produces quantization noise. A digital-to-analog converter (DAC) noiselessly converts the PDM signal into the analog replica, to aid in forming the error signal. In a particular embodiment of the invention, the resonator includes a recursive analog transversal filter with delays and linear weighting elements for linearity and high operating speed. The ADC may be in a high-speed system such as a radar.
摘要翻译： Σ-Δ（SIGMA DELTA）模数转换器（ADC）接受频带限制的模拟信号，并从其中减去输出脉冲或幅度密度调制（ADM）信号的模拟副本，以产生误差信号。 误差信号由具有非延迟正向路径和抽头非累积延迟线的模拟滤波器或谐振器处理，以及耦合到抽头的相加的反馈和前馈权重，从而产生谐振信号。 ADC处理谐振信号，产生ADM信号。 ADC不期望地产生量化噪声。 数模转换器（DAC）无声地将PDM信号转换成模拟副本，以帮助形成误差信号。 在本发明的特定实施例中，谐振器包括具有延迟的递归模拟横向滤波器和用于线性和高操作速度的线性加权元件。 ADC可以在诸如雷达的高速系统中。
-
公开(公告)号：US08294524B2
公开(公告)日：2012-10-23
申请号：US12645475
申请日：2009-12-22
申请人： Leopold E. Pellon
发明人： Leopold E. Pellon
IPC分类号： H03B9/14
CPC分类号： H03M1/662 , H04B1/0007 , H04B1/40
摘要： A representative integrated circuit comprises a clock signal generator that generates a clock signal, a code pattern generator that generates digital pattern data based on the clock signal, and a transversal digital-to-analog conversion (T-DAC) unit that includes a plurality of registers and a unary modulator (Umod) array. The T-DAC unit provides frequency selection ranges covering wide operational bands based on the digital pattern data and the clock signal.
摘要翻译： 代表性的集成电路包括产生时钟信号的时钟信号发生器，基于时钟信号产生数字图形数据的代码图形发生器和包括多个数字模拟转换（T-DAC）单元的横向数模转换（T-DAC）单元 寄存器和一元调制器（Umod）阵列。 T-DAC单元提供基于数字图形数据和时钟信号覆盖广泛运行频段的频率选择范围。
-
公开(公告)号：US20100166123A1
公开(公告)日：2010-07-01
申请号：US12645474
申请日：2009-12-22
IPC分类号： H04L27/00
摘要： A representative integrated circuit comprises a clock signal generator that generates a clock signal, a code pattern generator that generates digital pattern data based on the clock signal, and multiple traversal local oscillator synthesizers that are coupled in a cascaded configuration. Each traversal local oscillator synthesizer includes a transversal digital-to-analog conversion (T-DAC) unit that includes a plurality of registers and a unary modulator (Umod) array. The T-DAC provides frequency selection ranges covering wide operational bands based on the digital pattern data and the clock signal.
摘要翻译： 代表性的集成电路包括产生时钟信号的时钟信号发生器，基于时钟信号产生数字图形数据的代码图形发生器和以级联配置耦合的多个遍历本地振荡器合成器。 每个遍历本地振荡器合成器包括包括多个寄存器和一元调制器（Umod）阵列的横向数模转换（T-DAC）单元。 T-DAC提供基于数字图形数据和时钟信号覆盖宽范围操作频段的频率选择范围。
-
公开(公告)号：US5608400A
公开(公告)日：1997-03-04
申请号：US519593
申请日：1995-08-24
申请人： Leopold E. Pellon
发明人： Leopold E. Pellon
摘要： A sigma-delta analog-to-digital converter (10) provides high loop gain for suppression of noise components by use of a regenerative feedback loop or resonator (50), which produces a comb resonance response 212), embedded in the main degenerative feedback loop (48). The main loop includes an ADC (32) which samples at a clock frequency, which in turn defines a Nyquist frequency. The main loop also includes a DAC (38) which has a transfer function (42), which is equalized by a filter (44). The resonator (50) includes a low-pass filter (52) which matches the equalized main loop transfer function, a DC block (56), and a null filter (54) which nulls the resonator gain at the comb peak which lies above the Nyquist frequency. The open-loop transfer function of the regenerative loop (50) is set to unity gain and 0.degree..+-.N 360.degree. phase at the frequency of the analog input signal. A multipole embodiment (510) has multiple regenerative loops (55o) which produce multipole noise rejection (642). Resonators (751) are used in other .SIGMA..DELTA. ADCs (790, 890).
摘要翻译： Σ-Δ模数转换器（10）通过使用嵌入在主退化反馈中的再生反馈回路或共振器（50）提供用于抑制噪声分量的高环路增益，其产生梳状共振响应212） 循环（48）。 主回路包括ADC（32），其以时钟频率进行采样，其又限定奈奎斯特频率。 主回路还包括具有传递函数（42）的DAC（38），其由滤波器（44）均衡。 谐振器（50）包括与均衡的主环路传递函数相匹配的低通滤波器（52），DC块（56）和零滤波器（54），其使位于 奈奎斯特频率 再生回路（50）的开环传递函数设定为模数输入信号频率下的单位增益和0°+/- N 360°相位。 多极实施例（510）具有产生多极噪声抑制的多个再生回路（55o）（642）。 谐振器（751）用于其他SIGMA DELTA ADC（790,890）。
-
公开(公告)号：US5274386A
公开(公告)日：1993-12-28
申请号：US900826
申请日：1992-06-17
申请人： Leopold E. Pellon
发明人： Leopold E. Pellon
CPC分类号： H01Q3/2629 , G01S3/30 , G01S7/2813
摘要： A beamformer for a main antenna and a plurality of auxiliary antennas converts the main and each of the auxiliary signals to digital form. Each of the real and auxiliary digital signals is applied to a pair of real multipliers, in which multiplication by beamforming weights is performed, to produce one weighted real main signal, one weighted imaginary main signal, and a plurality of weighted real and weighted imaginary auxiliary signals. The weighted real main and auxiliary signals are summed together by a cascade of summers, and the weighted imaginary main and auxiliary signals are likewise summed together by another summed cascade. A digital product detector is connected to the output of each summer cascade. The first digital product detector produces in-phase and quadrature components of real detected signals, and the second digital product detector produces in-phase and quadrature components of imaginary detected signals. The quadrature imaginary detected signals are subtracted from the in-phase real detected signals, and the in-phase imaginary detected signals are added to the quadrature real detected signals, to produce signals corresponding to the signals received by the main antenna with reduced sidelobes.
摘要翻译： 用于主天线和多个辅助天线的波束形成器将主信号和每个辅助信号转换成数字形式。 实数和辅助数字信号中的每一个被施加到一对实数乘法器，其中执行通过波束形成权重的乘法，以产生一个加权实数主信号，一个加权虚数主信号和多个加权实加权虚拟辅助 信号。 加权的实际主信号和辅助信号通过级联的加法相加在一起，并且加权的虚数主信号和辅助信号同样通过另一个相加的级联相加。 数字产品检测器连接到每个夏季级联的输出。 第一数字产品检测器产生实际检测信号的同相和正交分量，并且第二数字乘积检测器产生假想检测信号的同相和正交分量。 从同相实际检测信号中减去正交虚检测信号，并将同相虚检测信号加到正交实检测信号上，以产生与主天线接收的信号相对应的信号，并减少旁瓣。
-
-
-
-
-
-
-
-
搜索结果
9 条记录 (耗时 0.024 秒)
