公开(公告)号：US10411134B2

公开(公告)日：2019-09-10

申请号：US15934360

申请日：2018-03-23

Applicant: LG DISPLAY CO., LTD.

Inventor： Min-Cheol Kim ,  Youn-Gyoung Chang ,  Kwon-Shik Park ,  So-Hyung Lee ,  Ho-Young Jung ,  Ha-Jin Yoo ,  Jeong-Suk Yang

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/477 ,  H01L29/10 ,  H01L29/66

Abstract: A display device includes a gate electrode on a substrate of a semiconductor device, a gate insulating film over the gate electrode, an active layer comprising an oxide including indium, zinc and gallium on the gate insulating film, and overlapping the gate electrode, and a source electrode and a drain electrode that are spaced apart from each other, wherein the active layer is formed from a zinc-rich target material, and an atomic % ratio of indium, zinc and gallium in the active layer is different from an atomic % ratio of the zinc-rich target material.

公开(公告)号：US09735281B2

公开(公告)日：2017-08-15

申请号：US14937598

申请日：2015-11-10

Applicant: LG Display Co., Ltd.

Inventor： Min-Cheol Kim ,  Youn-Gyoung Chang ,  Kwon-Shik Park ,  So-Hyung Lee ,  Ho-Young Jung ,  Ha-Jin Yoo ,  Jeong-Suk Yang

IPC: H01L29/12 ,  H01L29/786 ,  H01L21/02 ,  H01L21/477 ,  H01L29/10

CPC classification number: H01L29/7869 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/02667 ,  H01L21/477 ,  H01L29/1033 ,  H01L29/66969

Abstract: An oxide semiconductor crystallization method may include depositing an In—Ga—Zn oxide over the substrate while heating a substrate to a temperature of 200 to 300° C., and heat-treating the deposited In—Ga—Zn oxide at a temperature of 200 to 350° C., thereby forming an oxide semiconductor layer crystallized throughout an entire thickness thereof.

公开(公告)号：US20150187809A1

公开(公告)日：2015-07-02

申请号：US14582274

申请日：2014-12-24

Applicant: LG Display Co., Ltd.

Inventor： Min-Cheol Kim ,  Youn-Gyoung Chang ,  Kwon-Shik Park ,  So-Hyung Lee ,  Ho-Young Jung ,  Ha-Jin Yoo ,  Jeong-Suk Yang

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1288

Abstract: A method for manufacturing a thin film transistor (TFT) array substrate having enhanced reliability is disclosed. The method includes forming a multilayer structure including at least one first metal layer and a second metal layer made of copper, forming a first mask layer including a first mask area corresponding to a data line and a second mask area corresponding to an electrode pattern to overlap with an active layer, patterning the multilayer structure, thereby forming the data line constituted by the multilayer structure, patterning the second metal layer, thereby forming the electrode pattern constituted by the at least one first metal layer, forming a second mask layer to expose a portion of the electrode pattern corresponding to a channel area of the active layer, patterning the at least one first metal layer, thereby forming source and drain.

Abstract translation: 公开了一种制造具有增强的可靠性的薄膜晶体管（TFT）阵列基板的方法。 该方法包括形成包括至少一个第一金属层和由铜制成的第二金属层的多层结构，形成第一掩模层，第一掩模层包括对应于数据线的第一掩模区域和对应于电极图案的第二掩模区域以重叠 具有有源层，图案化多层结构，从而形成由多层结构构成的数据线，图案化第二金属层，从而形成由至少一个第一金属层构成的电极图案，形成第二掩模层以暴露 所述电极图案的部分对应于所述有源层的沟道区域，图案化所述至少一个第一金属层，从而形成源极和漏极。

公开(公告)号：US09343483B2

公开(公告)日：2016-05-17

申请号：US14582274

申请日：2014-12-24

Applicant: LG Display Co., Ltd.

Inventor： Min-Cheol Kim ,  Youn-Gyoung Chang ,  Kwon-Shik Park ,  So-Hyung Lee ,  Ho-Young Jung ,  Ha-Jin Yoo ,  Jeong-Suk Yang

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1288

Abstract: A method for manufacturing a thin film transistor (TFT) array substrate having enhanced reliability is disclosed. The method includes forming a multilayer structure including at least one first metal layer and a second metal layer made of copper, forming a first mask layer including a first mask area corresponding to a data line and a second mask area corresponding to an electrode pattern to overlap with an active layer, patterning the multilayer structure, thereby forming the data line constituted by the multilayer structure, patterning the second metal layer, thereby forming the electrode pattern constituted by the at least one first metal layer, forming a second mask layer to expose a portion of the electrode pattern corresponding to a channel area of the active layer, patterning the at least one first metal layer, thereby forming source and drain.

Abstract translation: 公开了一种制造具有增强的可靠性的薄膜晶体管（TFT）阵列基板的方法。 该方法包括形成包括至少一个第一金属层和由铜制成的第二金属层的多层结构，形成第一掩模层，第一掩模层包括对应于数据线的第一掩模区域和对应于电极图案的第二掩模区域以重叠 具有有源层，图案化多层结构，从而形成由多层结构构成的数据线，图案化第二金属层，从而形成由至少一个第一金属层构成的电极图案，形成第二掩模层以暴露 所述电极图案的部分对应于所述有源层的沟道区域，图案化所述至少一个第一金属层，从而形成源极和漏极。

公开(公告)号：US09960282B2

公开(公告)日：2018-05-01

申请号：US15643030

申请日：2017-07-06

Applicant: LG Display Co., Ltd.

Inventor： Min-Cheol Kim ,  Youn-Gyoung Chang ,  Kwon-Shik Park ,  So-Hyung Lee ,  Ho-Young Jung ,  Ha-Jin Yoo ,  Jeong-Suk Yang

IPC: H01L21/00 ,  H01L29/786 ,  H01L21/02 ,  H01L21/477 ,  H01L29/10

CPC classification number: H01L29/7869 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/02667 ,  H01L21/477 ,  H01L29/1033 ,  H01L29/66969

Abstract: A method for manufacturing a semiconductor device is discussed. The method includes forming a gate electrode on a substrate, forming a gate insulating film over the substrate, depositing an In—Ga—Zn oxide over the gate insulating film while heating the substrate to a temperature of 200 to 300° C., an atomic percent ratio of Zn in the In—Ga—Zn oxide as-deposited being higher than that of In or Ga, heat-treating the deposited In—Ga—Zn oxide at a temperature of 200 to 350° C., thereby forming an active layer crystallized throughout an entire thickness of the active layer, and forming a source electrode and a drain electrode.

公开(公告)号：US09722049B2

公开(公告)日：2017-08-01

申请号：US14138750

申请日：2013-12-23

Applicant: Intermolecular Inc. ,  LG Display Co., Ltd.

Inventor： Sang Lee ,  Khaled Ahmed ,  Youn-Gyoung Chang ,  Min-Cheol Kim ,  Minh Huu Le ,  Kwon-Sik Park ,  Woosup Shin

IPC: H01L21/00 ,  H01L29/66

CPC classification number: H01L29/66742 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: Embodiments described herein provide method for forming crystalline indium-gallium-zinc oxide (IGZO). A substrate is provided. A seed layer is formed above the substrate. The seed layer has a crystalline structure that is substantially dominant along the c-axis. An IGZO layer is formed above the seed layer. The seed layer may include zinc oxide. A stack of alternating seed layers and IGZO layers may be formed.