公开(公告)号：US20030031231A1

公开(公告)日：2003-02-13

申请号：US10083119

申请日：2002-02-27

Applicant: Korea Electronics Technology Institute

Inventor： Young-Hwan You ,  Cheol-Hee Park ,  Min-Chul Ju ,  Kee-Hyun Park ,  Jin-Woong Cho

IPC: H04B001/707

CPC classification number: H04B1/715 ,  H04B1/7143 ,  H04B2001/7154

Abstract: The present invention relates to an adaptive frequency hopping apparatus in a wireless personal area network (WPAN) system, wherein predetermined packets of data can be correctly transmitted by estimating the channel qualities of operating bands in advance and transmitting the packets through a proper band. The adaptive frequency hopping apparatus according to the present invention comprises a frequency table for monitoring each channel quality and storing and outputting information on each channel quality accumulated therein, a frequency hopping transceiver for generating and outputting a frequency pattern in accordance with predetermined rules, a link controller for generating an asynchronous connectionless (ACL) link in accordance with output signals of the frequency table and the frequency hopping transceiver and controlling selection of an operating mode between a channel avoidance scheme and a channel selection scheme, a packet handler for generating packet data by integrating a synchronous connection oriented (SCO) link and the ACL link inputted thereinto, a gaussian frequency shift keying (GFSK) modulator for performing GFSK modulation for signals outputted from the packet handler, a mode selector for selecting the operating mode between the channel avoidance scheme and the channel selection scheme in accordance with output signals of the frequency hopping transceiver and the link controller, a frequency synthesizer for synthesizing frequencies in accordance with output signals of the mode selector, a first multiplier for multiplying signals from outputted from the frequency synthesizer and the GFSK modulator and for outputting the multiplied signals as transmission signals, a second multiplier for multiplying the output signals of the frequency synthesizer by received signals, an RSSI detector for detecting a RSSI from output signals of the second multiplier, a GFSK demodulator for performing GFSK demodulation for the output signals of the second multiplier, a packet handler for restoring packet-type data from output signals of the GFSK demodulator, and a channel quality detector for estimating the channel quality by using the output signals of the RSSI detector and the packet handler, and storing it in the frequency table.

公开(公告)号：US20020064219A1

公开(公告)日：2002-05-30

申请号：US09728141

申请日：2000-12-01

Applicant: Korea Electronics Technology Institute

Inventor： Jong-Ho Paik ,  Young-Hwan You ,  Jin-Woong Cho ,  Won-Young Yang ,  Yong-Soo Cho

IPC: H04B001/38 ,  H04J001/12 ,  H04J003/10 ,  H04L005/16

CPC classification number: H04L5/143 ,  H04L5/023

Abstract: Disclosed is a zipper type Very high bit-rate Digital Subscriber Line (VDSL) system which comprises a transmitter including an inverse fast Fourier transformer for performing an inverse fast Fourier transform on input data, and a cyclic extension adder for adding a cyclic extension for each symbol to the data output from the inverse fast Fourier transformer and outputting the data to a transmission channel; and a receiver including a cyclic extension remover for removing the cyclic extension from the data received through the transmission channel, and a fast Fourier transformer for performing a fast Fourier transform on the data output from the cyclic extension remover. The cyclic extension adder copies a first predetermined number of data starting from the leading part of the input symbol data received from the inverse fast Fourier transformer into a first cyclic suffix for removing interference between symbols and maintaining orthogonality between sub-carriers; adds the first cyclic suffix to the end of the symbol data; copies a second predetermined number of data subsequent to the first predetermined number of data into a second cyclic suffix for maintaining orthogonality between upstream and downstream; and adds the second cyclic suffix to the end of the first cyclic suffix. According to the present invention, the cyclic extension system uses the CS alone to greatly reduce hardware size and delay, but it has the same transmission performance as the conventional system under normal channel environments. Furthermore, the present invention system in the asynchronous mode employs pulse shaping and windowing functions so as to enhance the performance as in the synchronous mode.

Abstract translation: 公开了一种拉链式非常高比特率数字用户线（VDSL）系统，其包括：发射机，包括用于对输入数据进行快速傅里叶逆变换的快速傅立叶逆变换器;以及循环扩展加法器，用于为每个 符号表示为从快速傅里叶逆变换器输出的数据，并将数据输出到传输通道; 以及接收机，包括用于从通过传输信道接收的数据中去除循环扩展的循环扩展删除器，以及用于对从循环扩展删除器输出的数据执行快速傅里叶变换的快速傅里叶变换器。 循环扩展加法器将从快速傅立叶逆变换逆变换器接收的输入符号数据的前导部分开始的第一预定数量的数据复制到第一循环后缀中，以消除符号之间的干扰并维持子载波之间的正交性; 将第一个循环后缀添加到符号数据的末尾; 将第一预定数量的数据之后的第二预定数量的数据复制到用于维持上游和下游之间的正交性的第二循环后缀中; 并将第二循环后缀添加到第一个循环后缀的末尾。 根据本发明，循环扩展系统仅使用CS来大大降低硬件尺寸和延迟，但在正常信道环境下它具有与常规系统相同的传输性能。 此外，本发明的异步模式系统采用脉冲整形和加窗功能，以提高同步模式下的性能。

公开(公告)号：US20040146116A1

公开(公告)日：2004-07-29

申请号：US10649647

申请日：2003-08-28

Applicant: Korea Electronics Technology Institute

Inventor： Sung-Jin Kang ,  Jin-Woong Cho ,  Cheol-Hee Park ,  Min-Chul Ju ,  Dae-Ki Hong ,  Kyeung-Hak Seo ,  Myoung-Jin Kim

IPC: H04K001/10 ,  H04L027/28

CPC classification number: H04J13/004 ,  H04J13/0077 ,  H04L1/0041 ,  H04L1/0061

Abstract: A constant amplitude coded bi-orthogonal demodulator demodulates the received constant amplitude bi-orthogonal modulated data, cancels the parity bits to generate the serial data, detects the occurrence of an error by dividing the demodulated data into a plurality of groups of data, outputs the serial data as demodulated data if an error does not occur, sequentially converts bit polarities of data of groups in which an error occurs if the error detector detects the error, compares distances between the received bi-orthogonal modulated data and the constant amplitude coded bi-orthogonal modulated data, and selects, as demodulated data, data of which corresponding bit polarities are changed according to the comparison results. According to the present invention, power consumption is reduced, a power amplifier can be manufactured at an inexpensive cost, interference robustness can be ensured, and data can be transmitted at a high transmission rate and a variable transmission rate.

Abstract translation: 一个恒定幅度编码的双正交解调器对接收到的恒幅双正交调制数据进行解调，取消奇偶校验位以产生串行数据，通过将解调数据分成多组数据来检测出错， 作为解调数据的串行数据如果不发生错误，则顺序地转换误差检测器检测到错误时发生错误的组的数据的位极性，比较接收到的双正交调制数据与恒幅编码的双向正交调制数据之间的距离， 正交调制数据，并根据比较结果选择相应位极性改变的数据作为解调数据。 根据本发明，能够降低能耗，能够以廉价的成本制造功率放大器，能够确保干扰稳定性，能够以高传输速度和可变传输速率传输数据。

公开(公告)号：US20030224822A1

公开(公告)日：2003-12-04

申请号：US10391023

申请日：2003-03-19

Applicant: Korea Electronics Technology Institute

Inventor： Cheol Hee Park ,  Min-Chul Ju ,  Dae-Ki Hong ,  Sung-Jin Kang ,  Jin-Woong Cho

IPC: H04B001/38

CPC classification number: H04J13/004 ,  H04B1/04 ,  H04B1/707 ,  H04B2201/70706

Abstract: An apparatus for transmitting data in a wireless communication system is disclosed. An apparatus for transmitting data in a wireless communication system according to the present invention includes a serial to parallel converter operable to transform serial data into parallel data; a summer operable to combine the parallel data after multiplying them by orthogonal code; a level clipper operable to remove a portion of the summed signal above and below a desired threshold range; and a quadrature phase shift keying(QPSK) modulator operable to change the phase of the clipped signal and to transfer the modulated signal therefrom. Thus, the present invention can embody high-speed data transfer rate in such a simple structure by combining a VSG method with an MC method to clip multi-level signals from the MC method and to maintain orthogonality of MC required in the VSG method.

Abstract translation: 公开了一种在无线通信系统中发送数据的装置。 根据本发明的用于在无线通信系统中发送数据的装置包括串行到并行转换器，其可操作以将串行数据转换为并行数据; 一个可以将并行数据乘以正交码的算术运算结果; 电平限幅器，其可操作以去除在期望阈值范围之上和之下的所述相加信号的一部分; 以及正交相移键控（QPSK）调制器，其可操作以改变限幅信号的相位并从其传送调制信号。 因此，本发明可以通过组合VSG方法与MC方法来以MC方法来克服多级信号并维持VSG方法所需的MC的正交性，从而以这种简单的结构体现高速数据传输速率。