公开(公告)号：US20020064219A1

公开(公告)日：2002-05-30

申请号：US09728141

申请日：2000-12-01

Applicant: Korea Electronics Technology Institute

Inventor： Jong-Ho Paik ,  Young-Hwan You ,  Jin-Woong Cho ,  Won-Young Yang ,  Yong-Soo Cho

IPC: H04B001/38 ,  H04J001/12 ,  H04J003/10 ,  H04L005/16

CPC classification number: H04L5/143 ,  H04L5/023

Abstract: Disclosed is a zipper type Very high bit-rate Digital Subscriber Line (VDSL) system which comprises a transmitter including an inverse fast Fourier transformer for performing an inverse fast Fourier transform on input data, and a cyclic extension adder for adding a cyclic extension for each symbol to the data output from the inverse fast Fourier transformer and outputting the data to a transmission channel; and a receiver including a cyclic extension remover for removing the cyclic extension from the data received through the transmission channel, and a fast Fourier transformer for performing a fast Fourier transform on the data output from the cyclic extension remover. The cyclic extension adder copies a first predetermined number of data starting from the leading part of the input symbol data received from the inverse fast Fourier transformer into a first cyclic suffix for removing interference between symbols and maintaining orthogonality between sub-carriers; adds the first cyclic suffix to the end of the symbol data; copies a second predetermined number of data subsequent to the first predetermined number of data into a second cyclic suffix for maintaining orthogonality between upstream and downstream; and adds the second cyclic suffix to the end of the first cyclic suffix. According to the present invention, the cyclic extension system uses the CS alone to greatly reduce hardware size and delay, but it has the same transmission performance as the conventional system under normal channel environments. Furthermore, the present invention system in the asynchronous mode employs pulse shaping and windowing functions so as to enhance the performance as in the synchronous mode.

Abstract translation: 公开了一种拉链式非常高比特率数字用户线（VDSL）系统，其包括：发射机，包括用于对输入数据进行快速傅里叶逆变换的快速傅立叶逆变换器;以及循环扩展加法器，用于为每个 符号表示为从快速傅里叶逆变换器输出的数据，并将数据输出到传输通道; 以及接收机，包括用于从通过传输信道接收的数据中去除循环扩展的循环扩展删除器，以及用于对从循环扩展删除器输出的数据执行快速傅里叶变换的快速傅里叶变换器。 循环扩展加法器将从快速傅立叶逆变换逆变换器接收的输入符号数据的前导部分开始的第一预定数量的数据复制到第一循环后缀中，以消除符号之间的干扰并维持子载波之间的正交性; 将第一个循环后缀添加到符号数据的末尾; 将第一预定数量的数据之后的第二预定数量的数据复制到用于维持上游和下游之间的正交性的第二循环后缀中; 并将第二循环后缀添加到第一个循环后缀的末尾。 根据本发明，循环扩展系统仅使用CS来大大降低硬件尺寸和延迟，但在正常信道环境下它具有与常规系统相同的传输性能。 此外，本发明的异步模式系统采用脉冲整形和加窗功能，以提高同步模式下的性能。