公开(公告)号：US20030131296A1

公开(公告)日：2003-07-10

申请号：US10284123

申请日：2002-10-31

Applicant: Korea Electronics Technology Institute

Inventor： Chang Won Park ,  Sung Ju Park ,  Hyung Su Lee ,  Jae Hoon Song

IPC: G01R031/28

CPC classification number: G01R31/318558 ,  G01R31/318508 ,  G01R31/318555 ,  G01R31/318563

Abstract: The present invention is an architecture of wrapped core linking module for accessing system on chip test which maintains compatibility of the IEEE 1149.1 standard with not only an IEEE 1149.1 boundary scan but also cores embodied by an IEEE P1500 wrapper and is able to systematically access the system on chip test with expandability. Thus, the wrapped core linking module in accordance with this present invention includes a link control register for storing the link control configuration between cores in the scan path of a system on chip according to control signals applied from the outside boundary, a link control register controller activating said link control register for controlling to shift and update the link configuration, a switch for setting the scan path between wrapped cores based on the link control configuration of said link control register and an output logic for connecting said link control register to the test data out (TDO) of the chip in case of testing the system on chip or cores of the system on chip.

Abstract translation: 本发明是用于访问片上测试的包裹核心链接模块的架构，其保持IEEE 1149.1标准与IEEE 1149.1边界扫描的兼容性，而且还包括由IEEE P1500封装件实现的核心，并且能够系统地访问系统 片上测试具有扩展性。 因此，根据本发明的被包装的核心链接模块包括链路控制寄存器，用于根据从外部边界施加的控制信号在片上系统的扫描路径中存储链路控制配置，链路控制寄存器控制器 激活所述链路控制寄存器用于控制移动和更新链路配置;基于所述链路控制寄存器的链路控制配置设置包裹核心之间的扫描路径的开关和用于将所述链路控制寄存器连接到测试数据的输出逻辑 （TDO）芯片的芯片上的芯片或芯片上的系统测试。