Invention Application
US20030131296A1 Wrapped core linking module for accessing system on chip test
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包裹核心链接模块,用于访问片上系统测试
- Patent Title: Wrapped core linking module for accessing system on chip test
- Patent Title (中): 包裹核心链接模块,用于访问片上系统测试
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Application No.: US10284123Application Date: 2002-10-31
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Publication No.: US20030131296A1Publication Date: 2003-07-10
- Inventor: Chang Won Park , Sung Ju Park , Hyung Su Lee , Jae Hoon Song
- Applicant: Korea Electronics Technology Institute
- Applicant Address: KR Gyeonggi-do
- Assignee: Korea Electronics Technology Institute
- Current Assignee: Korea Electronics Technology Institute
- Current Assignee Address: KR Gyeonggi-do
- Priority: KR2002-0000981 20020108
- Main IPC: G01R031/28
- IPC: G01R031/28

Abstract:
The present invention is an architecture of wrapped core linking module for accessing system on chip test which maintains compatibility of the IEEE 1149.1 standard with not only an IEEE 1149.1 boundary scan but also cores embodied by an IEEE P1500 wrapper and is able to systematically access the system on chip test with expandability. Thus, the wrapped core linking module in accordance with this present invention includes a link control register for storing the link control configuration between cores in the scan path of a system on chip according to control signals applied from the outside boundary, a link control register controller activating said link control register for controlling to shift and update the link configuration, a switch for setting the scan path between wrapped cores based on the link control configuration of said link control register and an output logic for connecting said link control register to the test data out (TDO) of the chip in case of testing the system on chip or cores of the system on chip.
Public/Granted literature
- US07117413B2 Wrapped core linking module for accessing system on chip test Public/Granted day:2006-10-03
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