公开(公告)号：US10288685B2

公开(公告)日：2019-05-14

申请号：US14266243

申请日：2014-04-30

申请人： Keysight Technologies, Inc.

发明人： John H. Guilford ,  Gidget A. Cathcart ,  Joseph E. Mueller ,  Gregory A. Hill ,  Steven Joseph Narciso

IPC分类号： G01R31/3183 ,  G01R31/319

摘要： An apparatus that moves stimulus data and response data between a memory and a device under test (DUT) over a plurality of data transfer banks. In a first mode the data transfer banks output the stimulus data to the DUT as respective independent banks of serial stimulus data channels, and write the response data into the memory responsive to data provided as respective independent banks of channels of serial data from the DUT. In a second mode the data transfer banks output the stimulus data to the DUT as a single bank of combined serial stimulus data channels, and write the response data into the memory responsive to the data provided as a combined single bank of channels of serial data from the DUT.

公开(公告)号：US20240305281A1

公开(公告)日：2024-09-12

申请号：US18120273

申请日：2023-03-10

申请人： Keysight Technologies, Inc.

发明人： Marc Almendros ,  Gidget A. Heintz ,  John H. Guilford

IPC分类号： H03K5/01

CPC分类号： H03K5/01 ,  H03K2005/00286

摘要： An integrated phase accumulator apparatus includes a first phase accumulator, a second phase accumulator, and a switch. The first phase accumulator is configured to accumulate a first phase increment over time and provide a first accumulated phase value for signal generation via a local oscillator at a first frequency. The second phase accumulator is configured to accumulate a second phase increment over time and provide a second accumulated phase value for signal generation via the local oscillator at a second frequency. The switch is configured to switch the integrated phase accumulation apparatus between the first frequency and the second frequency and between the second frequency and the first frequency so as to maintain a first continuous phase for the first frequency and a second continuous phase for the second frequency.

公开(公告)号：US20150316613A1

公开(公告)日：2015-11-05

申请号：US14266243

申请日：2014-04-30

申请人： Keysight Technologies, Inc.

发明人： John H. Guilford ,  Gidget A. Cathcart ,  Joseph E. Mueller ,  Gregory A. Hill ,  Steven Joseph Narciso

IPC分类号： G01R31/3183 ,  G01R31/319

CPC分类号： G01R31/31919 ,  G01R31/3183 ,  G01R31/318371 ,  G01R31/31926

摘要： An apparatus that moves stimulus data and response data between a memory and a device under test (DUT) over a plurality of data transfer banks. In a first mode the data transfer banks output the stimulus data to the DUT as respective independent banks of serial stimulus data channels, and write the response data into the memory responsive to data provided as respective independent banks of channels of serial data from the DUT. In a second mode the data transfer banks output the stimulus data to the DUT as a single bank of combined serial stimulus data channels, and write the response data into the memory responsive to the data provided as a combined single bank of channels of serial data from the DUT.

摘要翻译： 一种在多个数据传输库之间在存储器和待测器件（DUT）之间移动刺激数据和响应数据的装置。 在第一模式中，数据传输组将激励数据输出到DUT作为相应的独立的串行激励数据信道，并且响应于作为来自DUT的串行数据的独立通道组提供的数据，将响应数据写入存储器。 在第二模式中，数据传输组将激励数据输出到DUT作为单组合并的串行激励数据信道，并将响应数据写入到存储器中，该数据作为串行数据的组合信道组合提供， 被测件。

公开(公告)号：US09319050B1

公开(公告)日：2016-04-19

申请号：US14179736

申请日：2014-02-13

申请人： Keysight Technologies, Inc.

发明人： John H. Guilford ,  Gidget A. Cathcart ,  Steven Joseph Narciso

IPC分类号： H03L7/06

CPC分类号： H03L7/06 ,  H03L7/0812 ,  H03L7/091 ,  H03L7/22

摘要： An apparatus for phase alignment of clock signals includes a sampling circuit that samples a first clock signal on edges of a reference clock signal and that samples the reference clock signal on edges of the first clock signal, to generate a phase signal indicative of relative phase between the first clock signal and the reference clock signal. An alignment control circuit generates a control signal responsive to the phase signal, the control signal setting a phase shift direction for the first clock signal. A phase shifter shifts a phase of the first clock signal in the phase shift direction responsive to the control signal to align the phase of the first clock signal with a phase of the reference clock signal.

摘要翻译： 用于时钟信号的相位对准的装置包括采样电路，其对参考时钟信号的边缘进行采样第一时钟信号，并对第一时钟信号的边缘上的参考时钟信号进行采样，以产生指示相位相位的相位信号， 第一时钟信号和参考时钟信号。 对准控制电路响应于相位信号产生控制信号，控制信号为第一时钟信号设定相移方向。 移相器响应于控制信号在相移方向移动第一时钟信号的相位，以使第一时钟信号的相位与参考时钟信号的相位对准。