公开(公告)号：US20160329468A1

公开(公告)日：2016-11-10

申请号：US14902001

申请日：2014-06-23

Applicant: KONINKLIJKE PHILIPS N.V.

Inventor： Salman Akram ,  Quanbo Zou

IPC: H01L33/44 ,  H01L33/48 ,  H01L33/00 ,  H01L33/62

CPC classification number: H01L33/44 ,  H01L33/0066 ,  H01L33/0079 ,  H01L33/486 ,  H01L33/62 ,  H01L2933/0016 ,  H01L2933/0025 ,  H01L2933/0066

Abstract: Semiconductor LED layers are epitaxially gown on a patterned surface of a sapphire substrate (10). The patterned surface improves light extraction. The LED layers include a p-type layer and an n-type layer. The LED layers are etched to expose the n-type layer. One or more first metal layers are patterned to electrically contact the p-type layer and the n-type layer to form a p-metal contact (32) and an n-metal contact (33). A dielectric polymer stress-buffer layer (36) is spin-coated over the first metal layers to form a substantially planar surface over the first metal layers. The stress-buffer layer has openings exposing the p-metal contact and the n-metal contact. Metal solder pads (44, 45) are formed over the stress-buffer layer and electrically contact the p-metal contact and the n-metal contact through the openings in the stress-buffer layer. The stress-buffer layer acts as a buffer to accommodate differences in CTEs of the solder pads and underlying layers.

Abstract translation: 半导体LED层在蓝宝石衬底（10）的图案化表面上是外延的。 图案化表面改善了光提取。 LED层包括p型层和n型层。 蚀刻LED层以露出n型层。 将一个或多个第一金属层图案化以与p型层和n型层电接触以形成p金属接触（32）和n-金属接触（33）。 电介质聚合物应力缓冲层（36）被旋涂在第一金属层上以在第一金属层上形成基本平坦的表面。 应力缓冲层具有暴露p金属接触和n-金属接触的开口。 金属焊盘（44,45）形成在应力缓冲层之上，并通过应力缓冲层中的开口与p-金属触点和n-金属触点电接触。 应力缓冲层用作缓冲器以适应焊盘和下层的CTE的差异。

公开(公告)号：US20170358715A1

公开(公告)日：2017-12-14

申请号：US15581204

申请日：2017-04-28

Applicant: KONINKLIJKE PHILIPS N.V.

Inventor： Salman Akram ,  Quanbo Zou

IPC: H01L33/44 ,  H01L33/48 ,  H01L33/00 ,  H01L33/62

CPC classification number: H01L33/44 ,  H01L33/0066 ,  H01L33/0079 ,  H01L33/486 ,  H01L33/62 ,  H01L2933/0016 ,  H01L2933/0025 ,  H01L2933/0066

Abstract: Semiconductor LED layers are epitaxially grown on a patterned surface of a sapphire substrate. The patterned surface improves light extraction. The LED layers include a p-type layer and an n-type layer. The LED layers are etched to expose the n-type layer. One or more first metal layers are patterned to electrically contact the p-type layer and the n-type layer to form a p-metal contact and an n-metal contact. A dielectric polymer stress-buffer layer is spin-coated over the first metal layers to form a substantially planar surface over the first metal layers. The stress-buffer layer has openings exposing the p-metal contact and the n-metal contact. Metal solder pads are formed over the stress-buffer layer and electrically contact the p-metal contact and the n-metal contact through the openings in the stress-buffer layer. The stress-buffer layer acts as a buffer to accommodate differences in CTEs of the solder pads and underlying layers.

公开(公告)号：US09640729B2

公开(公告)日：2017-05-02

申请号：US14902001

申请日：2014-06-23

Applicant: KONINKLIJKE PHILIPS N.V.

Inventor： Salman Akram ,  Quanbo Zou

IPC: H01L33/44 ,  H01L33/62 ,  H01L33/48 ,  H01L33/00

CPC classification number: H01L33/44 ,  H01L33/0066 ,  H01L33/0079 ,  H01L33/486 ,  H01L33/62 ,  H01L2933/0016 ,  H01L2933/0025 ,  H01L2933/0066

Abstract: Semiconductor LED layers are epitaxially gown on a patterned surface of a sapphire substrate (10). The patterned surface improves light extraction. The LED layers include a p-type layer and an n-type layer. The LED layers are etched to expose the n-type layer. One or more first metal layers are patterned to electrically contact the p-type layer and the n-type layer to form a p-metal contact (32) and an n-metal contact (33). A dielectric polymer stress-buffer layer (36) is spin-coated over the first metal layers to form a substantially planar surface over the first metal layers. The stress-buffer layer has openings exposing the p-metal contact and the n-metal contact. Metal solder pads (44, 45) are formed over the stress-buffer layer and electrically contact the p-metal contact and the n-metal contact through the openings in the stress-buffer layer. The stress-buffer layer acts as a buffer to accommodate differences in CTEs of the solder pads and underlying layers.

公开(公告)号：US20150228849A1

公开(公告)日：2015-08-13

申请号：US14423162

申请日：2013-08-12

Applicant: KONINKLIJKE PHILIPS N.V.

Inventor： Quanbo Zou ,  Salman Akram ,  Jerome Chandra Bhat ,  Minh Ngoc Trieu ,  Robert Blank

IPC: H01L33/00 ,  H01L25/00 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00

Abstract: In one embodiment, a semiconductor device wafer (10) contains electrical components and has electrodes (28) on a first side of the device wafer (10). A transparent carrier wafer (30) is bonded to the first side of the device wafer (10) using a bonding material (32) (e.g., a polymer or metal). The second side of the device wafer (10) is then processed, such as thinned, while the carrier wafer (30) provides mechanical support for the device wafer (10). The carrier wafer (30) is then de-bonded from the device wafer (10) by passing a laser beam (46) through the carrier wafer (30), the carrier wafer (30) being substantially transparent to the wavelength of the beam. The beam impinges on the bonding material (32), which absorbs the beam's energy, to break the chemical bonds between the bonding material (32) and the carrier wafer (30). The released carrier wafer (30) is then removed from the device wafer (10), and the residual bonding material is cleaned from the device wafer (10).

Abstract translation: 在一个实施例中，半导体器件晶片（10）包含电子部件，并且在器件晶片（10）的第一侧上具有电极（28）。 使用接合材料（32）（例如聚合物或金属）将透明载体晶片（30）结合到器件晶片（10）的第一侧。 然后，当载体晶片（30）为器件晶片（10）提供机械支撑时，器件晶片（10）的第二侧被处理，例如变薄。 然后，通过使激光束（46）穿过载体晶片（30）将载体晶片（30）从器件晶片（10）去结合，载体晶片（30）对于波束的波长基本上是透明的。 光束撞击吸收光束能量的接合材料（32），以破坏接合材料（32）和载体晶片（30）之间的化学键。 然后将释放的载体晶片（30）从器件晶片（10）移除，并且从器件晶片（10）清除残留的接合材料。

公开(公告)号：US20160247969A1

公开(公告)日：2016-08-25

申请号：US15148135

申请日：2016-05-06

Applicant: KONINKLIJKE PHILIPS N.V.

Inventor： Quanbo Zou ,  Salman Akram ,  Jerome Chanra Bhat

IPC: H01L33/12 ,  H01L33/32 ,  H01L33/00 ,  H01L33/38 ,  H01L33/62 ,  H01L33/06 ,  H01L33/46

CPC classification number: H01L33/12 ,  H01L33/005 ,  H01L33/007 ,  H01L33/0079 ,  H01L33/06 ,  H01L33/32 ,  H01L33/38 ,  H01L33/46 ,  H01L33/62 ,  H01L2224/16 ,  H01L2924/1461 ,  H01L2933/0016 ,  H01L2933/0025 ,  H01L2933/0066 ,  H01L2924/00

Abstract: A method according to embodiments of the invention includes providing a wafer of semiconductor devices grown on a growth substrate. The wafer of semiconductor devices has a first surface and a second surface opposite the first surface. The second surface is a surface of the growth substrate. The method further includes bonding the first surface to a first wafer and bonding the second surface to a second wafer. In some embodiments, the first and second wafer each have a different coefficient of thermal expansion than the growth substrate. In some embodiments, the second wafer may compensate for stress introduced to the wafer of semiconductor devices by the first wafer

Abstract translation: 根据本发明的实施例的方法包括提供在生长衬底上生长的半导体器件的晶片。 半导体器件的晶片具有与第一表面相对的第一表面和第二表面。 第二表面是生长衬底的表面。 该方法还包括将第一表面结合到第一晶片并将第二表面结合到第二晶片。 在一些实施例中，第一和第二晶片各自具有与生长衬底不同的热膨胀系数。 在一些实施例中，第二晶片可以补偿由第​​一晶片引入半导体器件的晶片的应力