公开(公告)号：US20200044746A1

公开(公告)日：2020-02-06

申请号：US16599854

申请日：2019-10-11

Applicant: Juniper Networks, Inc.

Inventor： Naser Dalvand ,  Erik Johan Borberg ,  Brian Robert Kock

IPC: H04B10/60 ,  H04J14/02

Abstract: Described are various configurations for an amplifying optical demultiplexer. Various embodiments can receive an input signal comprising multiple sub-signals, and separate and amplify the signals within the demultiplexer. Some embodiments include a multistage demultiplexer with amplifiers located between a first and second stage. Some embodiments include a multistage demultiplexer with amplifiers located between a second and third stage.

公开(公告)号：US10998252B2

公开(公告)日：2021-05-04

申请号：US16791315

申请日：2020-02-14

Applicant: Juniper Networks, Inc.

Inventor： Erik Johan Norberg ,  Naser Dalvand ,  Gregory Alan Fish

IPC: H01L23/42 ,  H01L29/868 ,  H01L27/12 ,  H01L21/768 ,  H01L29/66 ,  H01L23/36

Abstract: The thermal impedance of p-i-n diodes integrated on semiconductor-on-insulator substrates can be reduced with thermally conducting vias that shunt heat across thermal barriers such as, e.g., the thick top oxide cladding often encapsulating the p-i-n diode. In various embodiments, one or more thermally conducting vias extend from a top surface of the intrinsic diode layer to a metal structure connected to the doped top layer of the diode, and/or from that metal structure down to at least the semiconductor device layer of the substrate.

公开(公告)号：US20200211923A1

公开(公告)日：2020-07-02

申请号：US16791315

申请日：2020-02-14

Applicant: Juniper Networks, Inc.

Inventor： Erik Johan Norberg ,  Naser Dalvand ,  Gregory Alan Fish

IPC: H01L23/42 ,  H01L23/36 ,  H01L27/12 ,  H01L21/768 ,  H01L29/66 ,  H01L29/868

Abstract: The thermal impedance of p-i-n diodes integrated on semiconductor-on-insulator substrates can be reduced with thermally conducting vias that shunt heat across thermal barriers such as, e.g., the thick top oxide cladding often encapsulating the p-i-n diode. In various embodiments, one or more thermally conducting vias extend from a top surface of the intrinsic diode layer to a metal structure connected to the doped top layer of the diode, and/or from that metal structure down to at least the semiconductor device layer of the substrate.

公开(公告)号：US20190273563A1

公开(公告)日：2019-09-05

申请号：US15910767

申请日：2018-03-02

Applicant: Juniper Networks, Inc.

Inventor： Naser Dalvand ,  Erik Johan Norberg ,  Brian Robert Koch

IPC: H04B10/60 ,  H04J14/02

Abstract: Described are various configurations for an amplifying optical demultiplexer. Various embodiments can receive an input signal comprising multiple sub-signals, and separate and amplify the signals within the demultiplexer. Some embodiments include a multistage demultiplexer with amplifiers located between a first and second stage. Some embodiments include a multistage demultiplexer with amplifiers located between a second and third stage.

公开(公告)号：US11215758B1

公开(公告)日：2022-01-04

申请号：US17022813

申请日：2020-09-16

Applicant: Juniper Networks, Inc.

Inventor： Naser Dalvand ,  Erik Johan Norberg

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/136

Abstract: A fabrication-tolerant non-linear waveguide taper for a waveguide transition can be designed by computing the scattering rate associated with the waveguide transition as a function of waveguide width of the waveguide taper for each of multiple sets of parameter values characterizing the waveguide transition (e.g., a set of nominal parameter values and sets of parameter values associated with process corners representing process variations from the nominal parameter values), determining an envelope of the computed width-dependent scattering rates, and computing a non-linear taper profile of the waveguide taper based on the envelope. Light propagation and coupling along the waveguide transition may further be computationally simulated for the multiple sets of parameter values to determine a minimum transmission value associated with the waveguide transition for a specified taper length, and/or to determine a minimum taper length at which the transmission values associated with the waveguide transition exceed a specified threshold transmission value.

公开(公告)号：US20210225732A1

公开(公告)日：2021-07-22

申请号：US17223167

申请日：2021-04-06

Applicant: Juniper Networks, Inc.

Inventor： Erik Johan Norberg ,  Naser Dalvand ,  Gregory Alan Fish

IPC: H01L23/42 ,  H01L21/768 ,  H01L23/36 ,  H01L27/12 ,  H01L29/66 ,  H01L29/868

Abstract: The thermal impedance of p-i-n diodes integrated on semiconductor-on-insulator substrates can be reduced with thermally conducting vias that shunt heat across thermal barriers such as, e.g., the thick top oxide cladding often encapsulating the p-i-n diode. In various embodiments, one or more thermally conducting vias extend from a top surface of the intrinsic diode layer to a metal structure connected to the doped top layer of the diode, and/or from that metal structure down to at least the semiconductor device layer of the substrate.

公开(公告)号：US10651110B1

公开(公告)日：2020-05-12

申请号：US16237300

申请日：2018-12-31

Applicant: Juniper Networks, Inc.

Inventor： Erik Johan Norberg ,  Naser Dalvand ,  Gregory Alan Fish

IPC: H01L23/42 ,  H01L29/868 ,  H01L27/12 ,  H01L21/768 ,  H01L29/66 ,  H01L23/36

Abstract: The thermal impedance of p-i-n diodes integrated on semiconductor-on-insulator substrates can be reduced with thermally conducting vias that shunt heat across thermal barriers such as, e.g., the thick top oxide cladding often encapsulating the p-i-n diode. In various embodiments, one or more thermally conducting vias extend from a top surface of the intrinsic diode layer to a metal structure connected to the doped top layer of the diode, and/or from that metal structure down to at least the semiconductor device layer of the substrate.