公开(公告)号：US06507509B1

公开(公告)日：2003-01-14

申请号：US09856913

申请日：2001-08-17

Applicant: Youichi Ohtsuka ,  Junichi Sone ,  Jaw-Shen Tsai ,  Takanari Yasui ,  Yasunobu Nakamura

Inventor： Youichi Ohtsuka ,  Junichi Sone ,  Jaw-Shen Tsai ,  Takanari Yasui ,  Yasunobu Nakamura

IPC: G11C1122

CPC classification number: B82Y10/00 ,  G11C11/22 ,  G11C11/5657 ,  H01L27/11502 ,  H01L29/7613 ,  H01L29/78391 ,  H01L29/7888

Abstract: High device reliability, a reduction in power consumption, and a high operation speed are achieved. When a predetermined bias voltage is applied between a source 1 and a drain 2 to change a gate voltage, a current discretely flows between the source 1 and the drain 2 in accordance with quantized electrostatic energy levels in an island electrode 3. The switching ON/OFF of the current between the source 1 and the drain 2 in this case is enabled by applying ½-electron charge to a gate. When the gate voltage induces polarization in a ferroelectric layer 6, its electric field is applied to the island electrode 3. The current between the source 1 and the drain 2 in this case can be measured with high sensitivity. Charge holding is carried out by the polarization in the ferroelectric layer 6, and stored data can be held even if power supply is cut off.

Abstract translation: 实现了高的设备可靠性，功耗的降低和高的运行速度。 当在源极1和漏极2之间施加预定的偏置电压以改变栅极电压时，根据岛状电极3中的量化的静电能量水平，电流离散地流过源极1和漏极2之间。开关导通/ 在这种情况下，源1和漏极2之间的电流的截止通过向栅极施加1/2电子电荷来实现。 当栅极电压在铁电层6中引起极化时，其电场被施加到岛状电极3.在这种情况下，源1和漏极2之间的电流可以高灵敏度地测量。 通过强电介质层6中的极化进行电荷保持，即使电源被切断，也可以保持存储的数据。

公开(公告)号：US4506166A

公开(公告)日：1985-03-19

申请号：US381653

申请日：1982-05-24

Applicant: Junichi Sone

Inventor： Junichi Sone

IPC: H03K3/38 ,  H03K5/04

CPC classification number: H03K3/38 ,  Y10S505/864

Abstract: A pulse generator utilizes a Josephson junction gate circuit having first and second control current paths for conducting control currents in opposite directions. An input signal applied to one of the control current paths will transform the Josephson junction device to the voltage state resulting in the leading edge of a pulse output from a branch circuit connected in parallel with the gate current path of the Josephson junction device, and the same input pulse passed through a delay circuit will be applied in the opposite direction to the other control current path to thereby switch the Josephson junction device back to the zero voltage state and cause the trailing edge of the pulse output. The delay device can be a .pi. circuit, a single additional Josephson junction device having its control current path connected either in series or in parallel with the one control current path of the first Josephson junction device, or a plurality of cascaded Josephson junction devices.

Abstract translation: 脉冲发生器利用具有第一和第二控制电流路径的约瑟夫逊结门电路，用于在相反的方向上传导控制电流。 施加到控制电流路径之一的输入信号将使约瑟夫逊结器件转换到电压状态，导致从与约瑟夫逊结器件的栅极电流通路并联连接的分支电路输出的脉冲的前沿，并且 通过延迟电路的相同输入脉冲将以与另一个控制电流路径相反的方向施加，从而将约瑟夫逊结器件切换回零电压状态，并引起脉冲输出的后沿。 延迟装置可以是pi电路，单个附加的约瑟夫逊结装置，其控制电流路径与第一约瑟夫逊结装置的一个控制电流路径串联或并联连接，或者多个级联的约瑟夫逊结装置。

公开(公告)号：US4489424A

公开(公告)日：1984-12-18

申请号：US376994

申请日：1982-05-11

Applicant: Junichi Sone

Inventor： Junichi Sone

IPC: H03B19/14 ,  H01L39/22 ,  H03K3/38 ,  H03K21/00 ,  H03K23/76 ,  H03K23/80 ,  H03K23/24

CPC classification number: H03K3/38 ,  H03K23/763 ,  Y10S505/83 ,  Y10S505/864

Abstract: A frequency divider is provided by coupling the gate current paths of a pair of Josephson junction gate circuits in parallel with the control current path of a third Josephson junction gate circuit being connected in series with the gate current path of one of the first pair of Josephson junctions. The gate current path of the third Josephson junction is connected in series with the control current path of the other of the first pair of Josephson junctions, and an input signal to be frequency divided is connected in common to the connection point of the control current path of the first Josephson junction and gate current path of the third Josephson junction. Current flowing through the control current path of the first Josephson junction will be at one-half the frequency of the input current. A plurality of frequency dividers may be cascaded to perform 1/2.sup.N frequency division.

Abstract translation: 通过将一对约瑟夫逊结门电路的栅极电流路径与第三约瑟夫逊结门电路的控制电流路径并联连接，与第一对约瑟夫森（Josephson）之一的栅极电流路径串联连接来提供分频器 路口 第三约瑟夫逊结的栅极电流路径与第一对约瑟夫逊结中的另一对的控制电流路径串联连接，并且待分频的输入信号共同连接到控制电流路径的连接点 的第一个约瑟夫逊结和第三个约瑟夫逊结的栅极电流路径。 流过第一约瑟夫逊结的控制电流路径的电流将为输入电流频率的一半。 多个分频器可以级联以执行1 / 2N分频。

公开(公告)号：US4611132A

公开(公告)日：1986-09-09

申请号：US754209

申请日：1985-07-11

Applicant: Junichi Sone

Inventor： Junichi Sone

IPC: H01L39/22 ,  H03K19/195

CPC classification number: H03K19/1956 ,  Y10S505/859

Abstract: A gate circuit includes a first group of N resistors connected together at one end to form a first input terminal for receiving an input current, a second group of N-1 resistors connected in series and connecting the other ends of the first group of resistors, N Josephson junction circuits each connected in series with one of the first group of resistors, a specific Josephson junction circuit coupled between a second input terminal and one end of the series connection of the second group of resistors, and an additional resistor connected between the second input terminal and a reference potential.

Abstract translation: 门电路包括在一端连接在一起以形成用于接收输入电流的第一输入端的第一组N个电阻器，串联连接并连接第一组电阻器的另一端的第二组N-1个电阻器， N个约瑟夫逊结电路各自与第一组电阻器中的一个串联连接，特定的约瑟夫逊结电路耦合在第二输入端子和第二组电阻器的串联连接的一端之间，以及连接在第二组电阻器之间的附加电阻器 输入端子和参考电位。

公开(公告)号：US4538077A

公开(公告)日：1985-08-27

申请号：US415877

申请日：1982-09-08

Applicant: Junichi Sone

Inventor： Junichi Sone

IPC: H03K19/195

CPC classification number: H03K19/1956 ,  Y10S505/859

Abstract: A circuit utilizing Josephson junctions to perform high speed logic gate switching functions. Three "Y" connected resistors have Josephson junction devices at their non-connected ends. The resistances of the resistors, the critical currents of the Josephson junctions, and the amplitudes of input currents to two of the resistor-Josephson junction connections are selected so that, when the input currents are applied at the same time, the third Josephson junction is switched to the voltage state and both input currents are derived from the third Josephson junction-resistor connection as an input current. In another embodiment, the basic circuit has additional resistor-Josephson junction input arms, producing an M/N logic gate function. In another embodiment, the resistors are ".DELTA." connected. The resulting logic gates have wide operational margins, high speed switching capabilities and small size.

Abstract translation: 利用约瑟夫逊结的电路执行高速逻辑门切换功能。 三个“Y”连接的电阻器在其非连接端具有约瑟夫逊结器件。 选择电阻器的电阻，约瑟夫逊结的临界电流以及到两个电阻 - 约瑟夫逊结连接点的输入电流的幅度，使得当输入电流同时施加时，第三约瑟夫逊结是 切换到电压状态，两个输入电流均作为输入电流从第三个约瑟夫逊结电阻连接导出。 在另一个实施例中，基本电路具有附加的电阻 - 约瑟夫逊结输入臂，产生M / N逻辑门功能。 在另一实施例中，电阻“DELTA”连接。 所产生的逻辑门具有广泛的操作裕度，高速切换能力和小尺寸。