公开(公告)号：US20130287390A1

公开(公告)日：2013-10-31

申请号：US13393066

申请日：2011-08-18

申请人： Junichi Abe ,  Hidemi Noguchi

发明人： Junichi Abe ,  Hidemi Noguchi

IPC分类号： H04B10/61

CPC分类号： H04B10/616 ,  H03H17/0202 ,  H03H2218/04 ,  H04B3/142 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03159 ,  H04L25/03178 ,  H04L2025/03401 ,  H04L2025/03636

摘要： In order to solve a problem of achieving distortion compensation with high accuracy, a digital filter device includes a first distortion compensation filter unit for conducting distortion compensation of first waveform distortion included in an inputted signal through digital signal processing, a first filter coefficient setting unit for setting a filter coefficient of the first distortion compensation filter unit, a second distortion compensation filter unit for compensating second waveform distortion included in a signal outputted from the first distortion compensation filter unit, and a second filter coefficient setting unit for setting a filter coefficient of the second distortion compensation filter unit based on the filter coefficient set by the first filter coefficient setting unit.

摘要翻译： 为了以高精度解决失真补偿的问题，数字滤波器装置包括：第一失真补偿滤波器单元，用于通过数字信号处理对包含在输入信号中的第一波形失真进行失真补偿，第一滤波器系数设定单元， 设置第一失真补偿滤波器单元的滤波器系数;第二失真补偿滤波器单元，用于补偿从第一失真补偿滤波器单元输出的信号中包括的第二波形失真;以及第二滤波器系数设置单元，用于设置滤波器系数 第二失真补偿滤波器单元，其基于由第一滤波器系数设置单元设置的滤波器系数。

公开(公告)号：US08681027B2

公开(公告)日：2014-03-25

申请号：US13521917

申请日：2011-02-24

申请人： Junichi Abe ,  Hidemi Noguchi

发明人： Junichi Abe ,  Hidemi Noguchi

IPC分类号： H03M1/10

CPC分类号： H04B10/695 ,  H03M1/1061 ,  H03M1/1235 ,  H04B10/60

摘要： A digital receiver includes: an analog-to-digital (AD) converter (102) for setting discrimination levels in accordance with a discrimination level control signal and converting an analog input signal into a digital signal based on the set discrimination levels; a discrimination level adjusting circuit (104) for generating the discrimination level control signal and outputting the discrimination level control signal to the AD converter; a signal quality monitoring portion (108) for generating a transfer function correction control signal, which is information about a transfer function of the AD converter; and a transfer function correcting circuit (106) for performing signal processing on the digital signal so as to cancel a gap between the transfer function of the AD converter and an initial transfer function based on the transfer function correction control signal.

摘要翻译： 数字接收机包括：模数（AD）转换器（102），用于根据鉴别电平控制信号设置识别电平，并根据所设置的辨别电平将模拟输入信号转换为数字信号; 判别电平调整电路（104），用于产生鉴别电平控制信号，并将识别电平控制信号输出到AD转换器; 信号质量监视部分（108），用于产生作为关于AD转换器的传递函数的信息的传递函数校正控制信号; 以及传递函数校正电路（106），用于对数字信号执行信号处理，以便基于传递函数校正控制信号消除AD转换器的传递函数与初始传递函数之间的间隙。

公开(公告)号：US20120280844A1

公开(公告)日：2012-11-08

申请号：US13521917

申请日：2011-02-24

申请人： Junichi Abe ,  Hidemi Noguchi

发明人： Junichi Abe ,  Hidemi Noguchi

IPC分类号： H03M1/06

CPC分类号： H04B10/695 ,  H03M1/1061 ,  H03M1/1235 ,  H04B10/60

摘要： A digital receiver includes: an analog-to-digital (AD) converter (102) for setting discrimination levels in accordance with a discrimination level control signal and converting an analog input signal into a digital signal based on the set discrimination levels; a discrimination level adjusting circuit (104) for generating the discrimination level control signal and outputting the discrimination level control signal to the AD converter; a signal quality monitoring portion (108) for generating a transfer function correction control signal, which is information about a transfer function of the AD converter; and a transfer function correcting circuit (106) for performing signal processing on the digital signal so as to cancel a gap between the transfer function of the AD converter and an initial transfer function based on the transfer function correction control signal.

摘要翻译： 数字接收机包括：模数（AD）转换器（102），用于根据鉴别电平控制信号设置识别电平，并根据所设置的辨别电平将模拟输入信号转换为数字信号; 判别电平调整电路（104），用于产生鉴别电平控制信号，并将识别电平控制信号输出到AD转换器; 信号质量监视部分（108），用于产生作为关于AD转换器的传递函数的信息的传递函数校正控制信号; 以及传递函数校正电路（106），用于对数字信号执行信号处理，以便基于传递函数校正控制信号消除AD转换器的传递函数与初始传递函数之间的间隙。

公开(公告)号：US08831081B2

公开(公告)日：2014-09-09

申请号：US13393066

申请日：2011-08-18

申请人： Junichi Abe ,  Hidemi Noguchi

发明人： Junichi Abe ,  Hidemi Noguchi

IPC分类号： H03H7/30 ,  H04B10/61 ,  H04B3/14 ,  H03H17/02 ,  H04L25/03

CPC分类号： H04B10/616 ,  H03H17/0202 ,  H03H2218/04 ,  H04B3/142 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03159 ,  H04L25/03178 ,  H04L2025/03401 ,  H04L2025/03636

摘要： In order to solve a problem of achieving distortion compensation with high accuracy, a digital filter device includes a first distortion compensation filter unit for conducting distortion compensation of first waveform distortion included in an inputted signal through digital signal processing, a first filter coefficient setting unit for setting a filter coefficient of the first distortion compensation filter unit, a second distortion compensation filter unit for compensating second waveform distortion included in a signal outputted from the first distortion compensation filter unit, and a second filter coefficient setting unit for setting a filter coefficient of the second distortion compensation filter unit based on the filter coefficient set by the first filter coefficient setting unit.

摘要翻译： 为了以高精度解决失真补偿的问题，数字滤波器装置包括：第一失真补偿滤波器单元，用于通过数字信号处理对包含在输入信号中的第一波形失真进行失真补偿;第一滤波器系数设定单元， 设置第一失真补偿滤波器单元的滤波器系数;第二失真补偿滤波器单元，用于补偿从第一失真补偿滤波器单元输出的信号中包括的第二波形失真;以及第二滤波器系数设置单元，用于设置滤波器系数 第二失真补偿滤波器单元，其基于由第一滤波器系数设置单元设置的滤波器系数。

公开(公告)号：US20120020677A1

公开(公告)日：2012-01-26

申请号：US13260297

申请日：2010-03-31

申请人： Hidemi Noguchi ,  junichi Abe ,  Tomoyuki Yamase ,  Yasushi Amamiya

发明人： Hidemi Noguchi ,  junichi Abe ,  Tomoyuki Yamase ,  Yasushi Amamiya

IPC分类号： H04B10/06

CPC分类号： H04L7/033 ,  H03L7/0816 ,  H04L7/0029 ,  H04L7/0037

摘要： To adequately perform sampling, a receiving device that solves problems that involve an increase in circuit area and an increase in cost, is provided.A/D converter 2 samples a coherent signal that is an analog signal in synchronization with a sampling clock signal so as to convert the analog signal into a digital signal. DSP 3 demodulates the digital signal converted by A/D converter 2 and computes a phase of the sampling clock signal in which an error rate of the digital signal is the minimum based on the demodulated digital signal. Sampling clock extraction circuit 4 extracts a clock signal having a symbol rate of the coherent signal therefrom. Phase adjustment circuit 5 adjusts the phase of the clock signal extracted by sampling clock extraction circuit 4 to the phase computed by DSP 3 and generates a clock signal having the adjusted phase as the sampling clock signal.

摘要翻译： 为了充分执行采样，提供了解决涉及电路面积增加和成本增加的问题的接收装置。 A / D转换器2与采样时钟信号同步地采样模拟信号的相干信号，以将模拟信号转换为数字信号。 DSP 3解调由A / D转换器2转换的数字信号，并且基于解调的数字信号计算数字信号的错误率为最小的采样时钟信号的相位。 采样时钟提取电路4从其中提取具有相干信号的符号速率的时钟信号。 相位调整电路5将由采样时钟提取电路4提取的时钟信号的相位调整为由DSP3计算的相位，并生成具有调整后的相位的时钟信号作为采样时钟信号。

公开(公告)号：US08861648B2

公开(公告)日：2014-10-14

申请号：US13260297

申请日：2010-03-31

申请人： Hidemi Noguchi ,  Junichi Abe ,  Tomoyuki Yamase ,  Yasushi Amamiya

发明人： Hidemi Noguchi ,  Junichi Abe ,  Tomoyuki Yamase ,  Yasushi Amamiya

IPC分类号： H04B17/00 ,  H04B3/46 ,  H03L7/081 ,  H04L7/033 ,  H04L7/00

CPC分类号： H04L7/033 ,  H03L7/0816 ,  H04L7/0029 ,  H04L7/0037

摘要： To adequately perform sampling, a receiving device that solves problems that involve an increase in circuit area and an increase in cost, is provided.A/D converter 2 samples a coherent signal that is an analog signal in synchronization with a sampling clock signal so as to convert the analog signal into a digital signal. DSP 3 demodulates the digital signal converted by A/D converter 2 and computes a phase of the sampling clock signal in which an error rate of the digital signal is the minimum based on the demodulated digital signal. Sampling clock extraction circuit 4 extracts a clock signal having a symbol rate of the coherent signal therefrom. Phase adjustment circuit 5 adjusts the phase of the clock signal extracted by sampling clock extraction circuit 4 to the phase computed by DSP 3 and generates a clock signal having the adjusted phase as the sampling clock signal.

摘要翻译： 为了充分执行采样，提供了解决涉及电路面积增加和成本增加的问题的接收装置。 A / D转换器2与采样时钟信号同步地采样模拟信号的相干信号，以将模拟信号转换为数字信号。 DSP 3解调由A / D转换器2转换的数字信号，并且基于解调的数字信号计算数字信号的错误率为最小的采样时钟信号的相位。 采样时钟提取电路4从其中提取具有相干信号的符号速率的时钟信号。 相位调整电路5将由采样时钟提取电路4提取的时钟信号的相位调整为由DSP3计算的相位，并生成具有调整后的相位的时钟信号作为采样时钟信号。

公开(公告)号：US20140232577A1

公开(公告)日：2014-08-21

申请号：US14343975

申请日：2012-06-05

申请人： Hidemi Noguchi

发明人： Hidemi Noguchi

IPC分类号： H03M1/00

CPC分类号： H03M1/002 ,  H03M1/005 ,  H03M1/1215 ,  H03M1/188

摘要： An analog-to-digital converter according to the present invention includes first and second analog-to-digital conversion cells (11, 12), control means (10) for, when a mode specifying signal MD indicates a first mode, generating a control signal that sets first and second input ranges to the same voltage range and sets first and second clocks to different phases, and when the mode specifying signal MD indicates a second mode, generating the control signal that sets the first and second input ranges to one continuous voltage range and sets the first and second clocks to the same phase, ADC cell control means (111) for controlling the voltage ranges of the first and second input ranges according to the control signal, and a sampling clock generation unit (112) that generates the first and second sampling clocks according to the control signal.

摘要翻译： 根据本发明的模拟 - 数字转换器包括第一和第二模数转换单元（11,12），控制装置（10），用于当模式指定信号MD指示第一模式时，产生控制 信号，其将第一和第二输入范围设置为相同的电压范围，并将第一和第二时钟设置为不同的相位，并且当模式指定信号MD指示第二模式时，生成将第一和第二输入范围设置为一个连续的控制信号 电压范围，并将第一和第二时钟设置为相同相位，ADC单元控制装置（111）用于根据控制信号控制第一和第二输入范围的电压范围;以及采样时钟生成单元（112），其生成 根据控制信号的第一和第二采样时钟。

公开(公告)号：US20130176609A1

公开(公告)日：2013-07-11

申请号：US13824813

申请日：2011-10-21

申请人： Hidemi Noguchi

发明人： Hidemi Noguchi

IPC分类号： G02F1/01

CPC分类号： G02F1/0121 ,  G02F1/0327 ,  G02F1/0356 ,  G02F2201/16 ,  H04B10/5561

摘要： To provide an optical phase modulation circuit and an optical phase modulation method capable of achieving a high-speed operation without increasing the power consumption. An optical phase modulation circuit according to the present invention includes an optical modulation unit 50 that includes a plurality of division electrodes 12 to 15 connected in tandem and generates a modulation signal by summing up optical signals modulated by using respective division electrodes, drive circuits 8 to 11 that drive the plurality of division electrodes, and a modulation timing control unit 60 that controls timings at which the optical signals are modulated in the plurality of division electrodes 12 to 15, by controlling an operation timing of the drive circuits 8 to 11.

摘要翻译： 提供能够在不增加功耗的情况下实现高速运行的光相位调制电路和光相位调制方法。 根据本发明的光相位调制电路包括光调制单元50，其包括串联连接的多个分割电极12至15，并且通过将通过使用各个分割电极调制的光信号相加产生调制信号，驱动电路8至 驱动多个分割电极的调制定时控制部60，以及通过控制驱动电路8〜11的动作定时来控制多个分割电极12〜15中的光信号的调制定时的调制定时控制部60。

公开(公告)号：US08415984B2

公开(公告)日：2013-04-09

申请号：US13121224

申请日：2009-11-02

申请人： Tomoyuki Yamase ,  Hidemi Noguchi

发明人： Tomoyuki Yamase ,  Hidemi Noguchi

IPC分类号： H03K5/00

CPC分类号： H03M1/0836 ,  H03K17/007 ,  H03M1/1215

摘要： Provided is an electronic circuit system which facilitates skew timing adjustment while preventing increase of power consumption. An electronic circuit system includes: a track hold circuit module formed by a hierarchical tree structure of track hold circuits which can track-hold an analog value of an analog signal; and a control signal generation module which supplies an operation control signal to each of the track hold circuits in the hierarchical tree structure. In the hierarchical tree structure, the number of track hold circuits of each of the hierarchies is stepwise changed from the first hierarchy of the input side to which an analog signal is inputted, toward the final hierarchy of the final output side as the number of hierarchies is increased.

摘要翻译： 提供一种电子电路系统，其有利于偏移定时调整，同时防止功耗的增加。 电子电路系统包括：跟踪保持电路模块，其由能够跟踪模拟信号的模拟值的跟踪保持电路的分级树结构形成; 以及控制信号生成模块，其以层次树结构向每个轨道保持电路提供操作控制信号。 在层次树结构中，每个层次的轨道保持电路的数量从输入模拟信号的输入侧的第一层级逐步地改变为最终输出侧的最终层级作为层次数 增加了。

公开(公告)号：US07605736B2

公开(公告)日：2009-10-20

申请号：US11214789

申请日：2005-08-31

申请人： Hidemi Noguchi

发明人： Hidemi Noguchi

IPC分类号： H03M1/12

CPC分类号： H03M1/1255

摘要： An A/D converter comprises a sample and hold circuit receiving a signal and operating based on a sampling clock, an A/D converting circuit converting an output signal of the sample and hold circuit to a digital signal, an A/D output determination circuit outputting a duty control signal based on the digital signal and a sampling clock generator adjusting a duty ratio of a sampling clock and applying the sampling clock to the sample and hold circuit.

摘要翻译： A / D转换器包括接收信号并基于采样时钟进行操作的采样和保持电路，将采样和保持电路的输出信号转换为数字信号的A / D转换电路，A / D输出确定电路 输出基于数字信号的占空比控制信号，以及采样时钟发生器，调整采样时钟的占空比并将采样时钟施加到采样和保持电路。