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公开(公告)号：US20050265149A1
公开(公告)日：2005-12-01
申请号：US10523386
申请日：2003-07-21
CPC分类号： G11B20/10027 , G11B7/005 , G11B20/10009 , G11B2020/1288 , G11B2220/2541
摘要： Optical disk systems comprising photo detectors (1) with variable gain amplifiers (10) and slicers (11) are provided with generators (12) in feedback paths between slicer (11) and amplifier (10) for controlling said amplifier (10) non-linearly. As a result, time constants of the control loop of said amplifier (10) which depend upon the level of the input signals are now compensated and the timing behavior of the control loop of said amplifier (10) has got a more continuous character. Said generator (12) comprises a converter (13) and is of low complexity and easy to integrate on a photo detector integrated-circuit together with said amplifier (10) and slicer (11) followed by a differential time delay detector (6). Said generator (12) comprises a further converter (14) with a capacitor (15) forming an integrator for making the mean value of the output voltage signal of said slicer (11) equal to zero.
摘要翻译： 包括具有可变增益放大器（10）和限幅器（11）的光电检测器（1）的光盘系统在限幅器（11）和放大器（10）之间的反馈路径中设置有发生器（12），用于控制所述放大器（10） 线性地 结果，依赖于输入信号的电平的所述放大器（10）的控制回路的时间常数现在被补偿，并且所述放大器（10）的控制回路的定时特性具有更连续的特性。 所述发生器（12）包括转换器（13），并且具有低复杂度并且易于与所述放大器（10）和限幅器（11）以及差分延时检测器（6）一起集成在光电检测器集成电路上。 所述发生器（12）包括具有形成用于使所述限幅器（11）的输出电压信号的平均值等于零的积分器的电容器（15）的另外的转换器（14）。
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公开(公告)号：US20060163607A1
公开(公告)日：2006-07-27
申请号：US10561302
申请日：2003-10-13
申请人： Johannes Voorman , Gerben De Jong
发明人： Johannes Voorman , Gerben De Jong
IPC分类号： H01L31/109 , H01L21/302
CPC分类号： H01L27/144
摘要： The efficiency of photo diodes is according to a basic idea improved by using them upside-down through letting the light (20) enter via the substrate layer (1), and by using the surface layer (3) as a mirror. Then, the epitaxial layer (2) has an approximately doubled chance to convert photons to electron-hole-pairs: either during a first pass when coming from the substrate layer (1) or during a second pass after being reflected at the surface layer (3). The surface layer (3) comprises metal stripes (6,7,8) and metal mirrors (9,10) and comprises metal areas (15,16) coupled to solders bumps (4,5) for precisely mounting said photo detector on a flexible printed-circuit board. The epitaxial layer (2) and areas (17,18,19) in the epitaxial layer (2) form electrodes of a first diode, and the epitaxial layer (2) and the substrate layer (1) form electrodes of a second diode which approximately doubles said efficiency again when adding the photocurrents of both diodes. A substrate layer (1) comprising silicon-on-insulator and/or an etch stopper can be easily made thinner by removing the silicon and/or by etching until said etch stopper.
摘要翻译： 光二极管的效率根据通过使光（20）通过衬底层（1）进入并通过使用表面层（3）作为反射镜而被颠倒使用而改进的基本思想。 然后，外延层（2）具有将光子转换成电子 - 空穴对的几乎双倍的机会：在来自基底层（1）的第一次通过期间或在表面层反射之后的第二遍期间 3）。 表面层（3）包括金属条纹（6,7,8）和金属反射镜（9,10），并且包括耦合到焊料凸点（4,5）的金属区域（15,16），用于将所述光电检测器精确地安装在 柔性印刷电路板。 外延层（2）和外延层（2）中的区域（17,18,19）形成第一二极管的电极，并且外延层（2）和衬底层（1）形成第二二极管的电极 当加入两个二极管的光电流时，再次使所述效率增加一倍。 通过去除硅和/或通过蚀刻直到所述蚀刻停止件，可以容易地使包含绝缘体上硅和/或蚀刻停止层的衬底层（1）变薄。
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3.发明申请公开(公告)号：US20060072393A1
公开(公告)日：2006-04-06
申请号：US10523385
申请日：2003-07-21
IPC分类号： G11B7/00
CPC分类号： G11B7/131 , G11B7/0901
摘要： Optical disk systems comprising photo detectors (1) for detecting optical disks comprising amplifiers and slicers (2-5) and delay-difference detectors (6) for detecting delay differences in sliced amplified detection signals are improved by installing delaylineless delay-difference detectors (6) comprising combinatorial-logic circuits (7,8) like inverters, ORs, NORs, ANDs, NANDs and sequential-logic circuits (11-18) like SetResetFlipFlops. Without the prior art delay lines, said delay-difference detectors (6) are of a lower complexity and low costly and can be well integrated. By introducing a first pair of sequential-logic circuits (11,12,15,16) for detecting delay differences between rising edges and a second pair of sequential-logic circuits (13,14,17,18) for detecting delay differences between falling edges, both kinds of edges are being used and the influence of time-jitter is less compared to the situation where just one kind of edge is used. Said delay-difference detector (6) further comprises an analog adder/subtracter (9) for adding/subtracting sequential-logic circuit output signals and low pass filter(s) (10) located before or after said adder/subtracter (9).
摘要翻译： 包括用于检测光盘的光检测器（1），包括用于检测分片放大检测信号中的延迟差的放大器和限幅器（2-5）和延迟差检测器（6），通过安装延迟无延迟差分检测器 ）包括类似反相器的组合逻辑电路（7,8），OR，NOR，AND，NAND和诸如SetResetFlipFlops的顺序逻辑电路（11-18）。 在没有现有技术的延迟线的情况下，所述延迟差检测器（6）具有较低的复杂性并且成本低且可以很好地集成。 通过引入用于检测上升沿之间的延迟差的第一对顺序逻辑电路（11,12,15,16）和用于检测下降沿之间的延迟差的第二对顺序逻辑电路（13,14,17,18） 边缘，正在使用两种边缘，并且与仅使用一种边缘的情况相比，时间抖动的影响较小。 所述延迟差检测器（6）还包括用于加/减顺序逻辑电路输出信号的模拟加法器/减法器（9）和位于所述加法器/减法器（9）之前或之后的低通滤波器（10）。
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4.发明申请公开(公告)号：US20050254828A1
公开(公告)日：2005-11-17
申请号：US10520228
申请日：2003-07-01
CPC分类号： H04B10/69 , G11B7/13 , G11B19/125
摘要： The optical signal receiving unit (10), which receives and processes an optical signal, can be programmed by the optical signal. The optical signal is detected by an optical sensor (20) and processed by a signal processor (40). The signal processor (40) has an operating mode, which is set by a programmable control unit (30). The control unit (30) is programmable by a program signal derived from the optical signal. In one embodiment the optical signal receiving unit (10) can be switched between two operating modes by a program switch signal provided at a program switch terminal (53). The apparatus (100) for reproducing information from an optical data carrier (101) comprises an optical signal receiving unit (10) according to the invention.
摘要翻译： 可以通过光信号对接收和处理光信号的光信号接收单元（10）进行编程。 光信号由光学传感器（20）检测并被信号处理器（40）处理。 信号处理器（40）具有由可编程控制单元（30）设置的操作模式。 控制单元（30）可通过从光信号导出的程序信号来编程。 在一个实施例中，光信号接收单元（10）可以通过在程序交换终端（53）处提供的程序切换信号在两种操作模式之间切换。 用于从光数据载体（101）再现信息的装置（100）包括根据本发明的光信号接收单元（10）。
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公开(公告)号：US20050012526A1
公开(公告)日：2005-01-20
申请号：US10501427
申请日：2002-12-12
CPC分类号： H03F3/45179 , H03F3/3022 , H03F3/45748 , H03F3/45941 , H03F2203/30015 , H03F2203/45008 , H03F2203/45082 , H03F2203/45292 , H03F2203/45681
摘要： An improved differential inverter comprising a differential inverter having a differential input for receiving a first input signal and a second input signal, said inverter further comprising a differential control input for receiving a first control signal and a second control signal. The improved differential inverter further comprises a differential output for transmitting a first output signal and a second output signal. The improved differential inverter further comprises a controlled bias generator that generates the second vector of input signals in response to a bias control signal. The control bias signal is generated at an output of a voltage divider coupled to the differential output of the differential inverter said bias control signal being indicative for a DC voltage of the of the differential output.
摘要翻译： 一种改进的差分逆变器，包括具有用于接收第一输入信号和第二输入信号的差分输入的差分反相器，所述反相器还包括用于接收第一控制信号和第二控制信号的差分控制输入。 改进的差分逆变器还包括用于发送第一输出信号和第二输出信号的差分输出。 改进的差分逆变器还包括受控偏置发生器，其响应于偏置控制信号产生输入信号的第二矢量。 控制偏置信号在耦合到差分逆变器的差分输出的分压器的输出处产生，所述偏置控制信号指示差分输出的直流电压。
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公开(公告)号：US20100148834A1
公开(公告)日：2010-06-17
申请号：US12448827
申请日：2008-01-04
申请人： Jan S. Vromans , Jan Dekkers , Gerben De Jong
发明人： Jan S. Vromans , Jan Dekkers , Gerben De Jong
IPC分类号： H03K5/12
CPC分类号： H03C3/04 , H03C5/00 , H03F1/3282
摘要： The present invention relates to a circuit arrangement and method of applying predistortion to a baseband signal used for modulating a pulse-shaped signal, wherein an envelope information of the baseband signal is detected and slewing distortions of the pulse-shaped signal are reduced by applying at least one of a phase modulation and a duty cycle 5 modulation to the baseband signal as additional predistortion in response to the detected envelope information. Thereby, slewing distortions in the pulse-shaped signal are removed or at least reduced.
摘要翻译： 本发明涉及一种将预失真应用于用于调制脉冲信号的基带信号的电路装置和方法，其中基带信号的包络信息被检测并且脉冲信号的回转失真通过施加在 对基带信号进行相位调制和占空比5调制中的至少一个作为响应于检测到的包络信息的附加预失真。 因此，脉冲形信号中的回转失真被去除或至少减少。
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公开(公告)号：US20070052451A1
公开(公告)日：2007-03-08
申请号：US11530092
申请日：2006-09-08
IPC分类号： H03K5/22
CPC分类号： H03F3/45179 , H03F3/3022 , H03F3/45748 , H03F3/45941 , H03F2203/30015 , H03F2203/45008 , H03F2203/45082 , H03F2203/45292 , H03F2203/45681
摘要： An improved differential inverter comprising a differential inverter having a differential input for receiving a first input signal and a second input signal, said inverter further comprising a differential control input for receiving a first control signal and a second control signal. The improved differential inverter further comprises a differential output for transmitting a first output signal and a second output signal. The improved differential inverter further comprises a controlled bias generator that generates the second vector of input signals in response to a bias control signal. The control bias signal is generated at an output of a voltage divider coupled to the differential output of the differential inverter said bias control signal being indicative for a DC voltage of the of the differential output.
摘要翻译： 一种改进的差分逆变器，包括具有用于接收第一输入信号和第二输入信号的差分输入的差分反相器，所述反相器还包括用于接收第一控制信号和第二控制信号的差分控制输入。 改进的差分逆变器还包括用于发送第一输出信号和第二输出信号的差分输出。 改进的差分逆变器还包括受控偏置发生器，其响应于偏置控制信号产生输入信号的第二矢量。 控制偏置信号在耦合到差分逆变器的差分输出的分压器的输出处产生，所述偏置控制信号指示差分输出的直流电压。
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公开(公告)号：US20070042783A1
公开(公告)日：2007-02-22
申请号：US10558726
申请日：2004-05-26
IPC分类号： H04Q7/20
摘要： A receiver (10) is arranged to simultaneously receive at least a first (S1) radio frequency signal having a first frequency band (1) and a second radio frequency signal (S3) having a second frequency band (3) that is at least partly overlapping the first frequency band (1). The receiver has frequency down-conversion means (32,33) for frequency down converting the at least first (S1) and second radio frequency signals (S3) to at least a first (S2) and a second (S4) lower frequency signal and multiplexing means (34) for sequentially multiplexing the at least first (S2) and second lower frequency signals (S4) into a frequency multiplexed signal (S5).
摘要翻译： 接收器（10）被布置成同时接收具有第一频带（1）的第一（S 1）射频信号和具有第二频带（3）的第二射频信号（S 3） 至少部分地与第一频带（1）重叠。 接收机具有频率下变频装置（32,33），用于将至少第一（S 1）和第二射频信号（S 3）降频转换成至少第一（S 2）和第二（S 4） 低频信号和用于将至少第一（S 2）和第二低频信号（S 4）顺序多路复用为频率复用信号（S 5）的复用装置（34）。
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公开(公告)号：US08068540B2
公开(公告)日：2011-11-29
申请号：US12161926
申请日：2007-01-18
申请人： Gerben De Jong , Jan Vromans
发明人： Gerben De Jong , Jan Vromans
IPC分类号： H03K7/08
CPC分类号： H04L25/4902 , H03F3/189 , H03F3/217 , H03K7/08 , H04L25/4921 , H04L25/4923 , H04L27/361 , H04L27/367 , H04L2025/03363
摘要： A system and method for Cartesian modulation achieved via generation of a three-level pulse width modulated signal. The system in overview comprises two binary pulse width modulated signal generators receiving signals related to the in-phase and quadrature components of a base-band signal and a combination and amplification stage that combines the signals provided by the two binary pulse width modulated signal generators. The binary pulse width modulated signal generators contain at least one signal comparator and at least one base-band pre-distortion element. The signals related to the in-phase and quadrature components of the base-band signal may be; the positive or negative parts of the in-phase component, the positive or negative parts of the quadrature component, the absolute value or sign of the in-phase component, or the absolute value or sign of the quadrature component. These signals may be distorted by a base-band pre-distortion element before being coupled to the comparators.
摘要翻译： 通过产生三电平脉宽调制信号实现笛卡尔调制的系统和方法。 该系统概括地包括两个二进制脉宽调制信号发生器，其接收与基带信号的同相和正交分量相关的信号，以及组合由两个二进制脉宽调制信号发生器提供的信号的组合和放大级。 二进制脉宽调制信号发生器包含至少一个信号比较器和至少一个基带预失真元件。 与基带信号的同相和正交分量相关的信号可以是; 同相分量的正或负部分，正交分量的正或负部分，同相分量的绝对值或符号，或正交分量的绝对值或符号。 在耦合到比较器之前，这些信号可能被基带预失真元件失真。
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公开(公告)号：US20050286394A1
公开(公告)日：2005-12-29
申请号：US10531012
申请日：2003-09-19
CPC分类号： H03F1/32 , G11B7/0053 , G11B7/1263 , G11B7/13 , H03F1/3211 , H03G7/06
摘要： An electronic circuit is provided which can autonomously handle an input current (Ii) having a relatively wide dynamic range without being overdriven. The electronic circuit comprises an amplifier stage (AMPST) having an input (IP) for receiving the input current (Ii) and an output (OP) for supplying an output current (Io), such that, during operation, the strength of the output current (Io) increases in response to an increasing strength of the input current (Ii) as long as the strength of the input current (Ii) has not exceeded an input reference level. The strength of the output current (Io) is kept approximately constant when the strength of the input current (Ii) has exceeded the input reference level but has not exceeded a further input reference level. The strength of the output current (Io) decreases in response to an increasing strength of the input current (Ii) when the strength of the input current (Ii) has exceeded the further input reference level. The amplifier stage (AMPST) may comprise a current mirror (CM) having an input which forms the input (IP), an output which forms the output (OP), and a common node (cn). The amplifier stage (AMPST) further comprises first control means (FCM) having an input connected to the input (EP), and an output connected to the common node (cn). First control means (FCM) controls a current (I2) to the common node (cn) and a voltage (Vcn) at the common node (cn). The first control means (FCM) comprises limiting means (LMT) for limiting the current (I2) when the value of the input current (Ii) has exceeded the input reference level. Then both the input and the output currents (Ii and Io) are limited. In order to avoid a saturation situation of a current source (Is) which supplies a current (I) to the input (EP), the amplifier stage (AMPST) may comprise second control means (SCM) for supplying a compensation current (ICMP) to the input (IP) when the input signal (Ii) has exceeded the input reference level. The current mirror (CM) comprises first (CP1) and second (CP2) current paths which form the core of the current mirror (CM), as is generally known. The decrease in response to an increasing strength of the input current (Ii) when the strength of the input current (Ii) has exceeded the further input reference level is implemented by a third current path (CP3) which takes away current from the second current path (CP2). Optionally, to avoid that the value of the output current (Io) can become too low, a fourth current path (CP4) may be implemented which applies current to the second current path (CP2). The inventive electronic circuit may be advantageously applied in all electronic systems (like CD-apparatus) which need means to limit a maximum output signal.
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