公开(公告)号：US20250113618A1

公开(公告)日：2025-04-03

申请号：US18887167

申请日：2024-09-17

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Kentaro MIURA ,  Masahiro WATABE

IPC: H01L27/12 ,  H01L29/786

Abstract: A semiconductor device according to an embodiment of the present invention includes: a first semiconductor layer; a first gate electrode; a first gate insulating layer; a first insulating layer above the first gate electrode; a first electrode overlapping the first semiconductor layer, and electrically connected to the first semiconductor layer; a second semiconductor layer above the first insulating layer and made of a different material from the first semiconductor layer; a second gate electrode; a second gate insulating layer; a second electrode overlapping the second semiconductor layer, and electrically connected to the second semiconductor layer; and a first metal nitride layer between the second semiconductor layer and the second electrode, wherein the second semiconductor layer is polycrystalline, and an etching rate of the second semiconductor layer with respect to an etchant including phosphoric acid as a main component is less than 3 nm/min at 40° C.

公开(公告)号：US20250113543A1

公开(公告)日：2025-04-03

申请号：US18895479

申请日：2024-09-25

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Kentaro MIURA ,  Akihiro HANADA ,  Masahiro WATABE

IPC: H01L29/786 ,  H01L29/423

Abstract: A semiconductor device according to an embodiment of the present invention includes an oxide semiconductor layer having a polycrystalline structure and including an impurity region containing an impurity element, a gate electrode over the oxide semiconductor layer, an insulating layer between the oxide semiconductor layer and the gate electrode, a first contact hole penetrating the insulating layer and exposing the impurity region, a second contact hole penetrating at least the insulating layer and having a greater depth than the first contact hole, and a connection wiring electrically connecting the impurity region to a layer which is exposed in the second contact hole through the first contact hole and the second contact hole. The connection wiring includes a first conductive layer and a second conductive layer on the first conductive layer. A portion of the first conductive layer that is exposed from the second conductive layer contains the impurity element.

公开(公告)号：US20250113542A1

公开(公告)日：2025-04-03

申请号：US18887091

申请日：2024-09-17

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Kentaro MIURA ,  Akihiro HANADA ,  Takaya TAMARU ,  Masahiro WATABE

IPC: H01L29/786

Abstract: A semiconductor device comprises a first insulating layer; an oxide semiconductor layer having a polycrystalline structure on the first insulating layer; a gate insulating layer on the semiconductor oxide layer; a buffer layer on the gate insulating layer; a gate wiring on the buffer layer; and a second insulating layer on the gate wiring. The oxide semiconductor layer has a first region, a second region and a third region aligned toward a first direction. An electrical resistivity of the second region is higher than an electrical resistivity of the first region and lower than an electrical resistivity of the third region. A sheet resistance of the third region is less than 1000 ohm/square.

公开(公告)号：US20230292551A1

公开(公告)日：2023-09-14

申请号：US18176503

申请日：2023-03-01

Applicant: Japan Display Inc.

Inventor： Masashi TSUBUKU ,  Takeshi SAKAI ,  Kentaro MIURA ,  Hajime WATAKABE ,  Takaya TAMARU ,  Hiroshi TABATAKE ,  Yutaka UMEDA

IPC: H10K59/121

CPC classification number: H10K59/1213 ,  H01L27/1255

Abstract: A display device includes a light-emitting element; a first transistor and a second transistor connected in series between the light-emitting element and a driving power line; a third transistor electrically connected to a gate electrode of the first transistor; and a fourth transistor connected in parallel between a drain electrode of the first transistor and the light-emitting element, wherein a ratio of a channel width W1 to a channel length L1 of the first transistor (a W1/L1 ratio) and a ratio of a channel width W2 to a channel length L2 of the second transistor (a W2/L2 ratio) are larger than a ratio of a channel width W3 to a channel length L3 of the third transistor (a W3/L3 ratio) and a ratio of a channel width W4 to a channel length L4 of the fourth transistor (a W4/L4 ratio).

公开(公告)号：US20220231149A1

公开(公告)日：2022-07-21

申请号：US17575635

申请日：2022-01-14

Applicant: Japan Display Inc.

Inventor： Akihiro HANADA ,  Kentaro MIURA ,  Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Takeshi SAKAI

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/40 ,  H01L21/3115

Abstract: According to one embodiment, a method of manufacturing a semiconductor device comprises forming an oxide semiconductor layer, forming a gate insulating layer in contact with the oxide semiconductor layer and covering the oxide semiconductor layer, and forming a gate electrode on the gate insulating layer so as to overlap the oxide semiconductor layer, and injecting boron through the gate electrode and the gate insulating layer after forming the gate electrode, wherein a boron concentration included in a region of the gate insulating layer overlapping the gate electrode is in a range of 1E+16 [atoms/cm3] or more.

公开(公告)号：US20220367691A1

公开(公告)日：2022-11-17

申请号：US17660729

申请日：2022-04-26

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Kentaro MIURA ,  Akihiro HANADA ,  Takaya TAMARU

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/4757 ,  H01L21/4763 ,  H01L21/426 ,  H01L29/786

Abstract: According to one embodiment, a method of manufacturing a semiconductor device, includes forming a first insulating layer, an oxide semiconductor layer, a second insulating layer, a buffer layer and a metal layer sequentially on a base, forming a patterned resist on the metal layer, etching the buffer layer and the metal layer using the resist as a mask to expose an upper surface of the second insulating layer, reducing a volume of the resist to expose an upper surface along a side surface of the metal layer, etching the metal layer using the resist as a mask, to form a gate electrode and to expose an upper surface of the buffer layer, and carrying out ion implantation on the oxide semiconductor layer using the gate electrode as a mask.

公开(公告)号：US20220238558A1

公开(公告)日：2022-07-28

申请号：US17583231

申请日：2022-01-25

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Kentaro MIURA ,  Akihiro HANADA

IPC: H01L27/12 ,  H01L29/786

Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a polycrystalline silicon semiconductor, an oxide semiconductor, a gate electrode located directly above the oxide semiconductor, a first conductive layer in contact with the polycrystalline silicon semiconductor via a first contact hole, and in contact with the oxide semiconductor via a second contact hole and a second conductive layer stacked on the first conductive layer between the first contact hole and the second contact hole. The first conductive layer includes an extending portion extending from the second contact hole toward the gate electrode. The second conductive layer is not stacked on the extending portion. The first conductive layer is thinner than the second conductive layer.

公开(公告)号：US20220190164A1

公开(公告)日：2022-06-16

申请号：US17549882

申请日：2021-12-14

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Kentaro MIURA ,  Toshinari SASAKI ,  Takeshi SAKAI ,  Akihiro HANADA ,  Masashi TSUBUKU

IPC: H01L29/786 ,  H01L29/423

Abstract: According to one embodiment, a semiconductor device includes an oxide semiconductor. The oxide semiconductor includes a first edge portion and a second edge portion intersecting a gate electrode, a first area overlapping the gate electrode, a second area along the first edge portion, a third area along the second edge portion, a fourth area the first edge portion, a fifth area along the second edge portion, a sixth area surrounded by the first area, the second area and the third area, and a seventh area surrounded by the first area, the fourth area and the fifth area. The first area, the second area and the third area, the fourth area and the fifth area have a higher resistivity than those of the sixth area and the seventh area.

公开(公告)号：US20220181493A1

公开(公告)日：2022-06-09

申请号：US17542515

申请日：2021-12-06

Applicant: Japan Display Inc.

Inventor： Kentaro MIURA ,  Hajime WATAKABE ,  Ryo ONODERA

IPC: H01L29/786 ,  H01L29/66

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a first insulating layer above a polycrystalline silicon semiconductor, forming an oxide semiconductor on the first insulating layer, forming a second insulating layer on the oxide semiconductor, forming contact holes penetrating to the polycrystalline silicon semiconductor in insulating layers including the first insulating layer and the second insulating layer, forming a metal film on the second insulating layer, forming a patterned resist on the metal film, etching the metal film using the resist as a mask, performing ion implantation into the oxide semiconductor without removing the resist, and removing the resist.

公开(公告)号：US20220165826A1

公开(公告)日：2022-05-26

申请号：US17533127

申请日：2021-11-23

Applicant: Japan Display Inc.

Inventor： Akihiro HANADA ,  Kentaro MIURA ,  Hajime WATAKABE ,  Ryo ONODERA

IPC: H01L27/32 ,  H01L51/56

Abstract: According to one embodiment, in a display device, a first transistor includes a first semiconductor layer, in which a first source region includes a first region in contact a the first source electrode and a first drain region includes a second region in contact with a first drain electrode, the first source and drain regions, the first region, and the second region each include a first impurity element, and, in a region close to an interface between the first semiconductor layer and a first insulating layer, a concentration of the first impurity element included in the first and second regions is higher than a concentration of the first impurity element included in the first source region and the first drain region.