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公开(公告)号：US20170317082A1
公开(公告)日：2017-11-02
申请号：US15139365
申请日：2016-04-27
发明人： Brent R. Den Hartog , Eric J. Lukes , Matthew J. Paschal , Nghia V. Phan , Raymond A. Richetta , Patrick L. Rosno , Timothy J. Schmerbeck , Dereje G. Yilma
IPC分类号： H01L27/092 , H01L27/02 , H01L29/417 , H01L29/78
CPC分类号： H01L27/092 , H01L21/823475 , H01L27/0207 , H01L27/088 , H01L29/41725 , H01L29/7816
摘要： A circuit component comprises a row of transistors. The row may contain a first active FET with a source region and a drain region. The row may also contain a first active dummy FET that shares the source region and that also has a diffusion region. The row may also contain a second active FET and a second active dummy FET, positioned such that the active dummy FETs are located between the active FETs on the row. The row may also have an end positioned such that the first active dummy FET is between the end and the first active FET. A supply of current may be electrically connected to the source diffusion regions. A load region may be electrically connected to the drain region. The first active FET and the first active dummy FET may have gates that share a voltage source or that have their own voltage source.
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公开(公告)号：US10075157B1
公开(公告)日：2018-09-11
申请号：US15492677
申请日：2017-04-20
发明人： Brent R. Den Hartog , Eric J. Lukes , Matthew J. Paschal , Nghia V. Phan , Raymond A. Richetta , Patrick L. Rosno , Timothy J. Schmerbeck , Dereje G. Yilma
IPC分类号： H03B1/00 , H03K3/00 , H03K17/08 , H03K19/0175 , H03H11/30
CPC分类号： H03K19/017509 , H03K19/00315
摘要： Certain aspects of the present disclosure are directed to a circuit for driving a signal at an output node. The circuit generally includes a voltage divider network having a first terminal coupled to the output node. The circuit also includes a first transistor having a gate coupled to a second terminal of the voltage divider network and a plurality of transistors. A gate of each of the plurality of transistors may be coupled to a respective tap node of the voltage divider network, and the plurality of transistors may include a third transistor having a source coupled to a drain of the first transistor. The circuit may also include a second transistor coupled to the first transistor and having a gate coupled to an input node of the circuit.
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公开(公告)号：US09312860B1
公开(公告)日：2016-04-12
申请号：US14631993
申请日：2015-02-26
发明人： Matthew J. Paschal , Raymond A. Richetta , Patrick L. Rosno , Timothy J. Schmerbeck , Dereje G. Yilma
IPC分类号： H03K3/013 , H03K19/0185 , G06F17/50
CPC分类号： H03K19/018578 , G06F17/5045 , G06F2217/78 , G06F2217/82
摘要： A gated differential logic circuit can include a header device having a first terminal coupled to a supply voltage, and a second terminal; a second header device having a third terminal coupled to the supply voltage, and a fourth terminal; a footer device having a fifth terminal coupled to ground, and a sixth terminal; and a second footer device having a seventh terminal coupled to ground, and an eighth terminal. The circuit further includes a driver circuit having a first supply terminal coupled to the second terminal and a first ground terminal coupled to the sixth terminal, and a second driver circuit having a second supply terminal coupled to the fourth terminal and a second ground terminal coupled to the eighth terminal. A capacitor can couple the first supply terminal to the second ground terminal, while a second capacitor may couple the second supply terminal to the first ground terminal.
摘要翻译： 门控差分逻辑电路可以包括具有耦合到电源电压的第一端子的接头装置和第二端子; 具有耦合到所述电源电压的第三端子的第二插头装置和第四端子; 具有耦合到地的第五端子的第一端子和第六端子; 以及具有耦合到地的第七端子的第二脚踏装置和第八端子。 电路还包括具有耦合到第二端子的第一电源端子和耦合到第六端子的第一接地端子的驱动器电路，以及具有耦合到第四端子的第二电源端子的第二驱动器电路和耦合到 第八码头。 电容器可以将第一电源端子耦合到第二接地端子，而第二电容器可以将第二电源端子耦合到第一接地端子。
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公开(公告)号：US10211205B2
公开(公告)日：2019-02-19
申请号：US15139365
申请日：2016-04-27
发明人： Brent R. Den Hartog , Eric J. Lukes , Matthew J. Paschal , Nghia V. Phan , Raymond A. Richetta , Patrick L. Rosno , Timothy J. Schmerbeck , Dereje G. Yilma
IPC分类号： H01L27/092 , H01L27/02 , H01L29/417 , H01L29/78
摘要： A circuit component comprises a row of transistors. The row may contain a first active FET with a source region and a drain region. The row may also contain a first active dummy FET that shares the source region and that also has a diffusion region. The row may also contain a second active FET and a second active dummy FET, positioned such that the active dummy FETs are located between the active FETs on the row. The row may also have an end positioned such that the first active dummy FET is between the end and the first active FET. A supply of current may be electrically connected to the source diffusion regions. A load region may be electrically connected to the drain region. The first active FET and the first active dummy FET may have gates that share a voltage source or that have their own voltage source.
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公开(公告)号：US10079595B1
公开(公告)日：2018-09-18
申请号：US15806421
申请日：2017-11-08
发明人： Brent R. Den Hartog , Eric J. Lukes , Matthew J. Paschal , Nghia V. Phan , Raymond A. Richetta , Patrick L. Rosno , Timothy J. Schmerbeck , Dereje G. Yilma
IPC分类号： H03B1/00 , H03K3/00 , H03K17/08 , H03H11/30 , H03K19/0175
CPC分类号： H03K19/017509 , H03K19/00315
摘要： Certain aspects of the present disclosure are directed to a circuit for driving a signal at an output node. The circuit generally includes a voltage divider network having a first terminal coupled to the output node. The circuit also includes a first transistor having a gate coupled to a second terminal of the voltage divider network and a plurality of transistors. A gate of each of the plurality of transistors may be coupled to a respective tap node of the voltage divider network, and the plurality of transistors may include a third transistor having a source coupled to a drain of the first transistor. The circuit may also include a second transistor coupled to the first transistor and having a gate coupled to an input node of the circuit.
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6.发明申请公开(公告)号：US20160182018A1
公开(公告)日：2016-06-23
申请号：US14696300
申请日：2015-04-24
IPC分类号： H03K3/012
CPC分类号： H03K3/012 , H03K19/0019
摘要： A method and circuit are provided for implementing adaptive control for optimization of pulsed resonant drivers, and a design structure on which the subject circuit resides. Peak detectors are used to detect a positive or up level reached by a resonant clock and negative or down level reached by the resonant clock. Each detected levels is compared to a reference level to determine when to vary the turn off timing of a clock driver pull-up device and/or a clock driver pull-down device. A positive peak detector controls the turn off time of the pull-up device and a negative peak detector controls a turn off time of the pull-down device in the pulsed resonant driver.
摘要翻译： 提供了一种用于实现用于优化脉冲谐振驱动器的自适应控制的方法和电路，以及主题电路所在的设计结构。 峰值检测器用于检测谐振时钟达到的正或上电平，并通过谐振时钟达到负向或下降电平。 将每个检测到的电平与参考电平进行比较，以确定何时改变时钟驱动器上拉器件和/或时钟驱动器下拉器件的截止时序。 正峰值检测器控制上拉器件的关断时间，负峰值检测器控制脉冲谐振驱动器中下拉器件的关断时间。
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公开(公告)号：US09490775B2
公开(公告)日：2016-11-08
申请号：US14576517
申请日：2014-12-19
CPC分类号： H03K3/012 , H03K19/0019
摘要： A method and circuit are provided for implementing adaptive control for optimization of pulsed resonant drivers, and a design structure on which the subject circuit resides. Peak detectors are used to detect a positive or up level reached by a resonant clock and negative or down level reached by the resonant clock. Each detected levels is compared to a reference level to determine when to vary the turn off timing of a clock driver pull-up device and/or a clock driver pull-down device. A positive peak detector controls the turn off time of the pull-up device and a negative peak detector controls a turn off time of the pull-down device in the pulsed resonant driver.
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8.发明授权公开(公告)号：US09397638B2
公开(公告)日：2016-07-19
申请号：US14696300
申请日：2015-04-24
CPC分类号： H03K3/012 , H03K19/0019
摘要： A method and circuit are provided for implementing adaptive control for optimization of pulsed resonant drivers, and a design structure on which the subject circuit resides. Peak detectors are used to detect a positive or up level reached by a resonant clock and negative or down level reached by the resonant clock. Each detected levels is compared to a reference level to determine when to vary the turn off timing of a clock driver pull-up device and/or a clock driver pull-down device. A positive peak detector controls the turn off time of the pull-up device and a negative peak detector controls a turn off time of the pull-down device in the pulsed resonant driver.
摘要翻译： 提供了一种用于实现用于优化脉冲谐振驱动器的自适应控制的方法和电路，以及主题电路所在的设计结构。 峰值检测器用于检测谐振时钟达到的正或上电平，并通过谐振时钟达到负向或下降电平。 将每个检测到的电平与参考电平进行比较，以确定何时改变时钟驱动器上拉器件和/或时钟驱动器下拉器件的截止时序。 正峰值检测器控制上拉器件的关断时间，负峰值检测器控制脉冲谐振驱动器中下拉器件的关断时间。
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公开(公告)号：US20160182016A1
公开(公告)日：2016-06-23
申请号：US14576517
申请日：2014-12-19
IPC分类号： H03K3/012
CPC分类号： H03K3/012 , H03K19/0019
摘要： A method and circuit are provided for implementing adaptive control for optimization of pulsed resonant drivers, and a design structure on which the subject circuit resides. Peak detectors are used to detect a positive or up level reached by a resonant clock and negative or down level reached by the resonant clock. Each detected levels is compared to a reference level to determine when to vary the turn off timing of a clock driver pull-up device and/or a clock driver pull-down device. A positive peak detector controls the turn off time of the pull-up device and a negative peak detector controls a turn off time of the pull-down device in the pulsed resonant driver.
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