公开(公告)号：US20160171148A1

公开(公告)日：2016-06-16

申请号：US14919756

申请日：2015-10-22

Applicant: International Business Machines Corporation

Inventor： Markus M. Helms

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/5081

Abstract: The method includes identifying a register-transfer level design description for a design. The method further includes identifying one or more tests to perform on the register-transfer level design description. The method includes generating a table of commands from the one or more tests to perform on the register-transfer level design description. The method includes generating a register-transfer level design description from the table of commands for at least one of a set of components including: a test driver for the design, a monitor for the design, and a checker for the design, wherein the register-transfer level design description assigns commands in the generated table of commands to be performed by a corresponding component in the set of components. The method includes simulating the identified one or more tests utilizing the generated register-transfer level design descriptions for at least one of the test driver, the checker, and the monitor.

Abstract translation: 该方法包括识别用于设计的寄存器传送级设计描述。 该方法还包括识别在寄存器传送级别设计描述上执行的一个或多个测试。 所述方法包括从所述一个或多个测试中生成指令表以在所述寄存器传送级设计描述上执行。 该方法包括从用于一组组件中的至少一个的命令表生成寄存器传送级别设计描述，包括：用于设计的测试驱动器，用于设计的监视器和用于设计的检查器，其中寄存器 - 转移级别设计描述在生成的命令表中分配由组件中的相应组件执行的命令。 该方法包括使用针对测试驱动器，检验器和监视器中的至少一个的所生成的寄存器传送级设计描述来模拟所识别的一个或多个测试。

公开(公告)号：US10140217B1

公开(公告)日：2018-11-27

申请号：US15844564

申请日：2017-12-17

Applicant: International Business Machines Corporation

Inventor： Uwe Brandt ,  Frank S. Lehnert ,  Thomas G. Koehler ,  Markus M. Helms ,  Martin Recktenwald

IPC: G06F12/1027 ,  G06F12/128 ,  G06F12/1009 ,  G06F12/122

Abstract: The present disclosure relates to a method of operating a hierarchical translation lookaside buffer (TLB). The TLB comprises at least two TLB levels, wherein a given entry of the upper level TLB comprises a portion of bits for indicating related entries in the lower level TLB. The method comprises the following when a TLB miss is encountered for a requested first virtual address. A first table walk is performed to obtain the absolute memory address for the first virtual address. A logical tag is stored. The logical tag comprises the portion of bits that has been identified in association with the first table walk. In response to determining that a concurrent second table walk, of the ongoing first table walk, that has a second virtual address that addresses the same entry in the upper level TLB as the first virtual address is writing in the TLB, the stored logical tag may be incremented. And, the incremented logical tag and the obtained absolute memory address may be stored in the TLB.

公开(公告)号：US20160125055A1

公开(公告)日：2016-05-05

申请号：US14533265

申请日：2014-11-05

Applicant: International Business Machines Corporation

Inventor： Markus M. Helms ,  Christian Jacobi ,  Aditya N. Puranik ,  Parminder Singh

IPC: G06F17/30 ,  G06F17/27

Abstract: Embodiments of the present invention provide systems and methods for increasing the efficiency of data conversion in a coprocessor by using the statistical occurrence of data patterns to convert frequently occurring data patterns in one conversion cycle. In one embodiment, a coprocessor system is disclosed containing a converter engine, which includes a parser and a converter, an input buffer, and a result store. The input buffer is configured to transfer a set of source data to the converter engine, which converts the source data from first code format to a second code format, and sends the converted source data to the result store.

Abstract translation: 本发明的实施例提供了通过使用数据模式的统计发生来在一个转换周期中转换经常出现的数据模式来提高协处理器中的数据转换效率的系统和方法。 在一个实施例中，公开了一种包含转换器引擎的协处理器系统，转换器引擎包括解析器和转换器，输入缓冲器和结果存储器。 输入缓冲器被配置为将一组源数据传送到转换器引擎，转换器引擎将源数据从第一代码格式转换为第二代码格式，并将转换的源数据发送到结果存储。

公开(公告)号：US10915547B2

公开(公告)日：2021-02-09

申请号：US16536499

申请日：2019-08-09

Applicant: International Business Machines Corporation

Inventor： Markus M. Helms ,  Christian Jacobi ,  Aditya N. Puranik ,  Parminder Singh

IPC: G06F16/00 ,  G06F16/25

Abstract: Embodiments of the present invention provide systems and methods for increasing the efficiency of data conversion in a coprocessor by using the statistical occurrence of data patterns to convert frequently occurring data patterns in one conversion cycle. In one embodiment, a coprocessor system is disclosed containing a converter engine, which includes a parser and a converter, an input buffer, and a result store. The input buffer is configured to transfer a set of source data to the converter engine, which converts the source data from first code format to a second code format, and sends the converted source data to the result store.

公开(公告)号：US10733199B2

公开(公告)日：2020-08-04

申请号：US14533265

申请日：2014-11-05

Applicant: International Business Machines Corporation

Inventor： Markus M. Helms ,  Christian Jacobi ,  Aditya N. Puranik ,  Parminder Singh

IPC: G06F16/25

Abstract: Embodiments of the present invention provide systems and methods for increasing the efficiency of data conversion in a coprocessor by using the statistical occurrence of data patterns to convert frequently occurring data patterns in one conversion cycle. In one embodiment, a coprocessor system is disclosed containing a converter engine, which includes a parser and a converter, an input buffer, and a result store. The input buffer is configured to transfer a set of source data to the converter engine, which converts the source data from first code format to a second code format, and sends the converted source data to the result store.

公开(公告)号：US20160171141A1

公开(公告)日：2016-06-16

申请号：US14571454

申请日：2014-12-16

Applicant: International Business Machines Corporation

Inventor： Markus M. Helms

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/5081

Abstract: The method includes identifying a register-transfer level design description for a design. The method further includes identifying one or more tests to perform on the register-transfer level design description. The method includes generating a table of commands from the one or more tests to perform on the register-transfer level design description. The method includes generating a register-transfer level design description from the table of commands for at least one of a set of components including: a test driver for the design, a monitor for the design, and a checker for the design, wherein the register-transfer level design description assigns commands in the generated table of commands to be performed by a corresponding component in the set of components. The method includes simulating the identified one or more tests utilizing the generated register-transfer level design descriptions for at least one of the test driver, the checker, and the monitor.

公开(公告)号：US10417252B2

公开(公告)日：2019-09-17

申请号：US14931116

申请日：2015-11-03

Applicant: International Business Machines Corporation

Inventor： Markus M. Helms ,  Christian Jacobi ,  Aditya N. Puranik ,  Parminder Singh

IPC: G06F17/22 ,  G06F16/25 ,  G06F17/27

Abstract: Embodiments of the present invention provide systems and methods for increasing the efficiency of data conversion in a coprocessor by using the statistical occurrence of data patterns to convert frequently occurring data patterns in one conversion cycle. In one embodiment, a coprocessor system is disclosed containing a converter engine, which includes a parser and a converter, an input buffer, and a result store. The input buffer is configured to transfer a set of source data to the converter engine, which converts the source data from first code format to a second code format, and sends the converted source data to the result store.

公开(公告)号：US10127159B1

公开(公告)日：2018-11-13

申请号：US15648884

申请日：2017-07-13

Applicant: International Business Machines Corporation

Inventor： Uwe Brandt ,  Frank S. Lehnert ,  Thomas G. Koehler ,  Markus M. Helms ,  Martin Recktenwald

IPC: G06F12/1027 ,  G06F12/122 ,  G06F12/1009 ,  G06F12/128

Abstract: The present disclosure relates to a method of operating a hierarchical translation lookaside buffer (TLB). The TLB comprises at least two TLB levels, wherein a given entry of the upper level TLB comprises a portion of bits for indicating related entries in the lower level TLB. The method comprises the following when a TLB miss is encountered for a requested first virtual address. A first table walk is performed to obtain the absolute memory address for the first virtual address. A logical tag is stored. The logical tag comprises the portion of bits that has been identified in association with the first table walk. In response to determining that a concurrent second table walk, of the ongoing first table walk, that has a second virtual address that addresses the same entry in the upper level TLB as the first virtual address is writing in the TLB, the stored logical tag may be incremented. And, the incremented logical tag and the obtained absolute memory address may be stored in the TLB.

公开(公告)号：US09703909B2

公开(公告)日：2017-07-11

申请号：US14571454

申请日：2014-12-16

Applicant: International Business Machines Corporation

Inventor： Markus M. Helms

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/5081

Abstract: The method includes identifying a register-transfer level design description for a design. The method further includes identifying one or more tests to perform on the register-transfer level design description. The method includes generating a table of commands from the one or more tests to perform on the register-transfer level design description. The method includes generating a register-transfer level design description from the table of commands for at least one of a set of components including: a test driver for the design, a monitor for the design, and a checker for the design, wherein the register-transfer level design description assigns commands in the generated table of commands to be performed by a corresponding component in the set of components. The method includes simulating the identified one or more tests utilizing the generated register-transfer level design descriptions for at least one of the test driver, the checker, and the monitor.

公开(公告)号：US09589087B2

公开(公告)日：2017-03-07

申请号：US14919756

申请日：2015-10-22

Applicant: International Business Machines Corporation

Inventor： Markus M. Helms

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/5081

Abstract: The method includes identifying a register-transfer level design description for a design. The method further includes identifying one or more tests to perform on the register-transfer level design description. The method includes generating a table of commands from the one or more tests to perform on the register-transfer level design description. The method includes generating a register-transfer level design description from the table of commands for at least one of a set of components including: a test driver for the design, a monitor for the design, and a checker for the design, wherein the register-transfer level design description assigns commands in the generated table of commands to be performed by a corresponding component in the set of components. The method includes simulating the identified one or more tests utilizing the generated register-transfer level design descriptions for at least one of the test driver, the checker, and the monitor.

Abstract translation: 该方法包括识别用于设计的寄存器传送级设计描述。 该方法还包括识别在寄存器传送级别设计描述上执行的一个或多个测试。 所述方法包括从所述一个或多个测试中生成指令表以在所述寄存器传送级设计描述上执行。 该方法包括从用于一组组件中的至少一个的命令表生成寄存器传送级别设计描述，包括：用于设计的测试驱动器，用于设计的监视器和用于设计的检查器，其中寄存器 - 转移级别设计描述在生成的命令表中分配由组件中的相应组件执行的命令。 该方法包括使用针对测试驱动器，检验器和监视器中的至少一个的所生成的寄存器传送级设计描述来模拟所识别的一个或多个测试。