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公开(公告)号：US09858188B2
公开(公告)日：2018-01-02
申请号：US14733665
申请日：2015-06-08
IPC分类号： G06F12/08 , G06F12/0831 , G06F12/0862
CPC分类号： G06F12/0831 , G06F12/0862 , G06F2212/621 , Y02D10/13
摘要： Statistical data is used to enable or disable snooping on a bus of a processor. A command is received via a first bus or a second bus communicably coupling processor cores and caches of chiplets on the processor. Cache logic on a chiplet determines whether or not a local cache on the chiplet can satisfy a request for data specified in the command. In response to determining that the local cache can satisfy the request for data, the cache logic updates statistical data maintained on the chiplet. The statistical data indicates a probability that the local cache can satisfy a future request for data. Based at least in part on the statistical data, the cache logic determines whether to enable or disable snooping on the second bus by the local cache.
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2.发明授权公开(公告)号：US09372797B2
公开(公告)日：2016-06-21
申请号：US14176775
申请日：2014-02-10
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0862 , G06F2212/621 , Y02D10/13
摘要： Statistical data is used to enable or disable snooping on a bus of a processor. A command is received via a first bus or a second bus communicably coupling processor cores and caches of chiplets on the processor. Cache logic on a chiplet determines whether or not a local cache on the chiplet can satisfy a request for data specified in the command. In response to determining that the local cache can satisfy the request for data, the cache logic updates statistical data maintained on the chiplet. The statistical data indicates a probability that the local cache can satisfy a future request for data. Based at least in part on the statistical data, the cache logic determines whether to enable or disable snooping on the second bus by the local cache.
摘要翻译： 统计数据用于在处理器的总线上启用或禁用窥探。 通过第一总线或第二总线接收命令，该第一总线或第二总线在处理器上可通信地耦合处理器核和高速缓存。 小命令上的缓存逻辑确定小节上的本地缓存是否能够满足命令中指定的数据请求。 响应于确定本地高速缓存能够满足对数据的请求，高速缓存逻辑更新维护在该小区上的统计数据。 统计数据表示本地缓存可以满足将来的数据请求的概率。 至少部分地基于统计数据，高速缓存逻辑确定是否在本地高速缓存上启用或禁用第二总线上的窥探。
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3.发明申请公开(公告)号：US20150269076A1
公开(公告)日：2015-09-24
申请号：US14733665
申请日：2015-06-08
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0862 , G06F2212/621 , Y02D10/13
摘要： Statistical data is used to enable or disable snooping on a bus of a processor. A command is received via a first bus or a second bus communicably coupling processor cores and caches of chiplets on the processor. Cache logic on a chiplet determines whether or not a local cache on the chiplet can satisfy a request for data specified in the command. In response to determining that the local cache can satisfy the request for data, the cache logic updates statistical data maintained on the chiplet. The statistical data indicates a probability that the local cache can satisfy a future request for data. Based at least in part on the statistical data, the cache logic determines whether to enable or disable snooping on the second bus by the local cache.
摘要翻译： 统计数据用于在处理器的总线上启用或禁用窥探。 通过第一总线或第二总线接收命令，该第一总线或第二总线在处理器上可通信地耦合处理器核和高速缓存。 小命令上的缓存逻辑确定小节上的本地缓存是否能够满足命令中指定的数据请求。 响应于确定本地高速缓存能够满足对数据的请求，高速缓存逻辑更新维护在该小区上的统计数据。 统计数据表示本地缓存可以满足将来的数据请求的概率。 至少部分地基于统计数据，高速缓存逻辑确定是否在本地高速缓存上启用或禁用第二总线上的窥探。
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4.发明申请公开(公告)号：US20130205087A1
公开(公告)日：2013-08-08
申请号：US13679247
申请日：2012-11-16
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0811
摘要： A multiprocessor data processing system includes a plurality of cache memories including a cache memory. In response to the cache memory detecting a storage-modifying operation specifying a same target address as that of a first read-type operation being processed by the cache memory, the cache memory provides a retry response to the storage-modifying operation. In response to completion of the read-type operation, the cache memory enters a referee mode. While in the referee mode, the cache memory temporarily dynamically increases priority of any storage-modifying operation targeting the target address in relation to any second read-type operation targeting the target address.
摘要翻译： 多处理器数据处理系统包括包括高速缓存存储器的多个高速缓存存储器。 响应于高速缓冲存储器检测指定与由高速缓冲存储器处理的第一读取型操作相同的目标地址的存储修改操作，高速缓冲存储器为存储修改操作提供重试响应。 响应于完成读取型操作，缓存存储器进入裁判模式。 在裁判模式下，高速缓存存储器临时动态地增加针对目标地址的任何存储修改操作的优先级，这相对于针对目标地址的任何第二读取类型操作。
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公开(公告)号：US20190266093A1
公开(公告)日：2019-08-29
申请号：US16410279
申请日：2019-05-13
IPC分类号： G06F12/0831 , G06F12/0862
摘要： Statistical data is used to enable or disable snooping on a bus of a processor. A command is received via a first bus or a second bus communicably coupling processor cores and caches of chiplets on the processor. Cache logic on a chiplet determines whether or not a local cache on the chiplet can satisfy a request for data specified in the command. In response to determining that the local cache can satisfy the request for data, the cache logic updates statistical data maintained on the chiplet. The statistical data indicates a probability that the local cache can satisfy a future request for data. Based at least in part on the statistical data, the cache logic determines whether to enable or disable snooping on the second bus by the local cache.
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公开(公告)号：US10331563B2
公开(公告)日：2019-06-25
申请号：US15796507
申请日：2017-10-27
IPC分类号： G06F12/00 , G06F12/0831 , G06F12/0862
摘要： Statistical data is used to enable or disable snooping on a bus of a processor. A command is received via a first bus or a second bus communicably coupling processor cores and caches of chiplets on the processor. Cache logic on a chiplet determines whether or not a local cache on the chiplet can satisfy a request for data specified in the command. In response to determining that the local cache can satisfy the request for data, the cache logic updates statistical data maintained on the chiplet. The statistical data indicates a probability that the local cache can satisfy a future request for data. Based at least in part on the statistical data, the cache logic determines whether to enable or disable snooping on the second bus by the local cache.
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7.发明授权Forward progress mechanism for stores in the presence of load contention in a system favoring loads by state alteration 有权在存在负载争用的情况下，通过状态改变有利于负载的系统中的商店的前进进展机制公开(公告)号：US08806148B2
公开(公告)日：2014-08-12
申请号：US13679351
申请日：2012-11-16
发明人： Guy L. Guthrie , Hien M. Le , Hugh Shen , Jeff A. Stuecheli , Derek E Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F2212/1008 , G06F2212/1016
摘要： A multiprocessor data processing system includes a plurality of cache memories including a cache memory. The cache memory issues a read-type operation for a target cache line. While waiting for receipt of the target cache line, the cache memory monitors to detect a competing store-type operation for the target cache line. In response to receiving the target cache line, the cache memory installs the target cache line in the cache memory, and sets a coherency state of the target cache line installed in the cache memory based on whether the competing store-type operation is detected.
摘要翻译： 多处理器数据处理系统包括包括高速缓存存储器的多个高速缓存存储器。 缓存存储器为目标高速缓存行发出读取类型操作。 在等待接收目标高速缓存行的同时，高速缓冲存储器监视以检测目标高速缓存行的竞争存储类型操作。 响应于接收到目标高速缓存行，高速缓存存储器将目标高速缓存行安装在高速缓冲存储器中，并且基于是否检测到竞争存储类型操作来设置安装在高速缓冲存储器中的目标高速缓存行的一致性状态。
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8.发明授权公开(公告)号：US08799589B2
公开(公告)日：2014-08-05
申请号：US13679247
申请日：2012-11-16
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0811
摘要： A multiprocessor data processing system includes a plurality of cache memories including a cache memory. In response to the cache memory detecting a storage-modifying operation specifying a same target address as that of a first read-type operation being processed by the cache memory, the cache memory provides a retry response to the storage-modifying operation. In response to completion of the read-type operation, the cache memory enters a referee mode. While in the referee mode, the cache memory temporarily dynamically increases priority of any storage-modifying operation targeting the target address in relation to any second read-type operation targeting the target address.
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公开(公告)号：US09501411B2
公开(公告)日：2016-11-22
申请号：US14473687
申请日：2014-08-29
CPC分类号： G06F12/0833 , G06F9/467 , G06F12/0811 , G06F12/0815 , G06F12/0897 , G06F12/12 , G06F2212/283 , G06F2212/62 , G06F2212/621
摘要： In response to a transactional store request, the higher level cache transmits, to the lower level cache, a backup copy of an unaltered target cache line in response to a target real address hitting in the higher level cache, updates the target cache line with store data to obtain an updated target cache line, and records the target real address as belonging to a transaction footprint of the memory transaction. In response to a conflicting access to the transaction footprint prior to completion of the memory transaction, the higher level cache signals failure of the memory transaction to the processor core, invalidates the updated target cache line in the higher level cache, and causes the backup copy of the target cache line in the lower level cache to be restored as a current version of the target cache line.
摘要翻译： 响应于事务存储请求，较高级缓存响应于在较高级别高速缓存中击中的目标实际地址向低级缓存发送未改变的目标高速缓存行的备份副本，用存储器更新目标高速缓存行 数据以获得更新的目标高速缓存行，并将目标实际地址记录为属于存储器事务的事务占用。 响应于在内存事务完成之前对交易占用空间的冲突访问，较高级别的高速缓存指示对处理器核心的存储器事务的失败，使得较高级别高速缓存中的更新的目标高速缓存行无效，并导致备份副本 的目标缓存行将被还原为目标缓存行的当前版本。
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公开(公告)号：US10997075B2
公开(公告)日：2021-05-04
申请号：US16410279
申请日：2019-05-13
IPC分类号： G06F12/08 , G06F12/0831 , G06F12/0862
摘要： Statistical data is used to enable or disable snooping on a bus of a processor. A command is received via a first bus or a second bus communicably coupling processor cores and caches of chiplets on the processor. Cache logic on a chiplet determines whether or not a local cache on the chiplet can satisfy a request for data specified in the command. In response to determining that the local cache can satisfy the request for data, the cache logic updates statistical data maintained on the chiplet. The statistical data indicates a probability that the local cache can satisfy a future request for data. Based at least in part on the statistical data, the cache logic determines whether to enable or disable snooping on the second bus by the local cache.
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