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1.发明授权公开(公告)号：US11017137B2
公开(公告)日：2021-05-25
申请号：US16595451
申请日：2019-10-07
发明人： Chaitanya Ravindra Peddawad , Jeffrey Hemmett , Jason D. Morsey , Steven E. Washburn , Peter Elmendorf , Debjit Sinha , Kerim Kalafala
IPC分类号： G06F30/33 , G06F30/327 , G06F30/392 , G06F119/12
摘要： The efficiency of electronic design automation is increased by building, as an electronic data structure, a timing graph characterizing a putative integrated circuit design; identifying at least one of an edge and a node in the timing graph that requires canonical timing adjustment; and electronically calculating a deterministic timing adjustment for each of a plurality of corner cases. Based on the calculated deterministic timing adjustment for each of the plurality of corner cases, the canonical timing adjustment is determined for the at least one of an edge and a node; the canonical timing adjustment is applied to the timing graph; and the timing graph is updated based on the application of the canonical timing adjustment.
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公开(公告)号：US10970455B1
公开(公告)日：2021-04-06
申请号：US16777845
申请日：2020-01-30
IPC分类号： G06F30/398 , G06F119/12
摘要： Methods and apparatus for creating an improved VLSI design. In-context timing analysis of a nominal VLSI design is performed and at least one assigned apportionment adjustment is determined for a sub-block of the nominal VLSI design. One or more slack adjustments are derived for at least one port of the sub-block based on the at least one apportionment adjustment and the one or more slack adjustments are applied to the in-context timing analysis to simulate a post optimization version of the sub-block. The in-context timing analysis is repeated using the one or more applied slack adjustments to generate the improved VLSI design.
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公开(公告)号：US10747925B1
公开(公告)日：2020-08-18
申请号：US16257386
申请日：2019-01-25
发明人： Jeffrey Hemmett , Kerim Kalafala , Natesan Venkateswaran , Debjit Sinha , Eric Foreman , Chaitanya Ravindra Peddawad
IPC分类号： G06F9/455 , G06F17/50 , G06F30/3312 , G06F30/327 , G06F119/12
摘要： A system and method of performing variable accuracy incremental timing analysis in integrated circuit development includes generating a timing graph for interconnected components. The timing graph represents each pin as a node and each interconnection as an arc. A first node or arc is selected. First-level timing values are obtained for the first node or arc using a first timing model that provides a first level of accuracy. n timing models with corresponding n levels of accuracy are pre-selected. The first-level timing values are copied as second-level timing values and as timing values for every other one of the n levels of accuracy for the first node or arc. A second node or arc downstream from the first node or arc is selected. Second-level timing values for the second node or arc are obtained using a second timing model that provides a second level of accuracy.
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公开(公告)号：US20180239858A1
公开(公告)日：2018-08-23
申请号：US15436895
申请日：2017-02-20
发明人： Robert J. Allen , Nathan C. Buck , Eric A. Foreman , Jeffrey G. Hemmett , Kerim Kalafala , Gregory M. Schaeffer , Stephen G. Shuma , Debjit Sinha , Natesan Venkateswaran , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5022 , G06F17/505 , G06F17/5063 , G06F2217/84
摘要： Creating an integrated circuit with non-linear variations, the computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of one or more of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.
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公开(公告)号：US08589842B1
公开(公告)日：2013-11-19
申请号：US13673521
申请日：2012-11-09
发明人： Manjul Bhushan , Eric J. Fluhr , Stephen G. Shuma , Debjit Sinha , Chandramouli Visweswariah , James D. Warnock , Michael H. Wood
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/10 , G06F2217/84
摘要： An approach for performing device-based random variability modeling in timing analysis of a digital integrated circuit having a gate-level design and a device-level custom design is described. In one embodiment, an algorithm is derived from results of simulating the operational behavior of a representative digital integrated circuit. A timing analysis is performed on the device-level custom design part of the digital integrated circuit to obtain device-level random variability sensitivity values. A gate-level characterization is performed on the gate-level design part of the digital integrated circuit to obtain logic gate random variability sensitivity values. A timing analysis is performed on the digital integrated circuit as a function of both the device-level random variability sensitivity values and the logic gate random variability sensitivity values.
摘要翻译： 描述了在具有门级设计和设备级定制设计的数字集成电路的时序分析中执行基于设备的随机变异性建模的方法。 在一个实施例中，从模拟代表性数字集成电路的操作行为的结果导出算法。 在数字集成电路的器件级定制设计部分执行时序分析，以获得器件级随机变异灵敏度值。 在数字集成电路的门级设计部分执行门级特性以获得逻辑门随机变异灵敏度值。 作为器件级随机变异灵敏度值和逻辑门随机变异灵敏度值的函数，对数字集成电路执行时序分析。
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公开(公告)号：US20200242205A1
公开(公告)日：2020-07-30
申请号：US16257386
申请日：2019-01-25
发明人： Jeffrey Hemmett , Kerim Kalafala , Natesan Venkateswaran , Debjit Sinha , Eric Foreman , Chaitanya Ravindra Peddawad
IPC分类号： G06F17/50
摘要： A system and method of performing variable accuracy incremental timing analysis in integrated circuit development includes generating a timing graph for interconnected components. The timing graph represents each pin as a node and each interconnection as an arc. A first node or arc is selected. First-level timing values are obtained for the first node or arc using a first timing model that provides a first level of accuracy. n timing models with corresponding n levels of accuracy are pre-selected. The first-level timing values are copied as second-level timing values and as timing values for every other one of the n levels of accuracy for the first node or arc. A second node or arc downstream from the first node or arc is selected. Second-level timing values for the second node or arc are obtained using a second timing model that provides a second level of accuracy.
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公开(公告)号：US10387682B2
公开(公告)日：2019-08-20
申请号：US15616961
申请日：2017-06-08
摘要： Embodiments of the present invention disclose a method, computer program product, and system for parallel access to an electronic design automation (EDA) application. The computer receives a request to access an electronic design automation (EDA) application from at least two user computing device and authenticates a user associated with each of the requests from the at least two user computing devices to access the EDA application. The computer determines a level of access to be granted to each of the user of the at least two user computing devices and creates a parallel connection to each of the at least user computing device based on the determined level of access granted to each of the users. The computer retrieves data to be transmitted to each of the at least user computing device to be displayed on each of the user computing devices and stores the data in a memory unit.
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公开(公告)号：US20180357433A1
公开(公告)日：2018-12-13
申请号：US15616961
申请日：2017-06-08
CPC分类号： G06F21/629 , G06F17/5045 , G06F21/31 , H04L63/08 , H04L63/102
摘要： Embodiments of the present invention disclose a method, computer program product, and system for parallel access to an electronic design automation (EDA) application. The computer receives a request to access an electronic design automation (EDA) application from at least two user computing device and authenticates a user associated with each of the requests from the at least two user computing devices to access the EDA application. The computer determines a level of access to be granted to each of the user of the at least two user computing devices and creates a parallel connection to each of the at least user computing device based on the determined level of access granted to each of the users. The computer retrieves data to be transmitted to each of the at least user computing device to be displayed on each of the user computing devices and stores the data in a memory unit.
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公开(公告)号：US09940431B2
公开(公告)日：2018-04-10
申请号：US14990212
申请日：2016-01-07
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5031 , G06F2217/78 , G06F2217/84
摘要： A system to improve performance of a semiconductor chip design includes a hierarchical analysis module that determines a hierarchical arrangement of the semiconductor chip design. The hierarchical arrangement includes a plurality of arcs located at different levels internal to the semiconductor chip design. The different levels include a macro level, a unit level and a core level. The system further includes a timing/load analysis module that determines first timing characteristics of at least one first arc in the macro level based on a first load applied to the at least one first arc. The system further determines second timing characteristics of at least one second arc in at least one of the unit level and the core level based on the first timing characteristics, with a portion of the second timing characteristics determined irrespective of the first load.
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公开(公告)号：US09798843B2
公开(公告)日：2017-10-24
申请号：US14800059
申请日：2015-07-15
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A statistical timing analysis using statistical timing macro-models considering statistical timing value entries such as input slew and output load is disclosed. That statistical timing analysis calculates a statistical timing quantity based on statistical timing value entries based on a statistical timing (ST) macro-model of a selected macro of an integrated circuit (IC) design that includes statistical timing quantities as a function of deterministic timing value entries.
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