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1.发明申请公开(公告)号：US20210103637A1
公开(公告)日：2021-04-08
申请号：US16595451
申请日：2019-10-07
发明人： Chaitanya Ravindra Peddawad , Jeffrey Hemmett , Jason D. Morsey , Steven E. Washburn , Peter Elmendorf , Debjit Sinha , Kerim Kalafala
IPC分类号： G06F17/50
摘要： The efficiency of electronic design automation is increased by building, as an electronic data structure, a timing graph characterizing a putative integrated circuit design; identifying at least one of an edge and a node in the timing graph that requires canonical timing adjustment; and electronically calculating a deterministic timing adjustment for each of a plurality of corner cases. Based on the calculated deterministic timing adjustment for each of the plurality of corner cases, the canonical timing adjustment is determined for the at least one of an edge and a node; the canonical timing adjustment is applied to the timing graph; and the timing graph is updated based on the application of the canonical timing adjustment.
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公开(公告)号：US10565336B2
公开(公告)日：2020-02-18
申请号：US15988125
申请日：2018-05-24
摘要： A system and method to perform an integrated circuit design involves selecting a net among a plurality of nets of the integrated circuit design as a victim net. Each net connects a pair of nodes of the integrated circuit design and each node represents a logic element of the integrated circuit design. The method also includes determining aggressor nets among the plurality of nets for the victim net and determining a corresponding weight value for each of the aggressor nets and, for each of the aggressor nets, multiplying the coupled noise originating from the aggressor net with the corresponding weight value to obtain a weighted coupled noise value. A cumulative coupled noise value is obtained for the victim net as a sum of the weighted coupled noise values associated with each of the aggressor nets. A result of the integrated circuit design is provided for fabrication into an integrated circuit.
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公开(公告)号：US10248753B2
公开(公告)日：2019-04-02
申请号：US15288260
申请日：2016-10-07
IPC分类号： G06F17/50
摘要： A method, system, and computer product for performing a coupled noise analysis in an integrated circuit (IC) design include copying one or more victim circuit sections of a victim circuit in the IC design, generating a blockage circuit section that represents a blockage aggressor circuit in the IC design, using the copied one or more victim circuit sections of the victim circuit, determining at least one subcircuit from the blockage circuit section, selecting, for a victim pin on the victim circuit, a power-driven virtual node on the at least one subcircuit, applying a power source to the power-driven virtual node on the at least one subcircuit, calculating a coupled noise at the victim pin contributed by the at least one subcircuit in response to the power source being applied, comparing the coupled noise to a threshold noise level, and altering the IC design when the coupled noise exceeds the threshold noise level.
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4.发明申请公开(公告)号：US20180101636A1
公开(公告)日：2018-04-12
申请号：US15288260
申请日：2016-10-07
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5009 , G06F17/5036 , G06F17/5077
摘要： A method, system, and computer product for performing a coupled noise analysis in an integrated circuit (IC) design include copying one or more victim circuit sections of a victim circuit in the IC, generating a blockage circuit section that represents a blockage aggressor circuit in the IC, using the copied one or more victim sections of the victim circuit, determining at least one subcircuit from the blockage circuit section, selecting, for a victim pin on the victim circuit, a power-driven virtual node on the at least one subcircuit, applying a power source to the power-driven virtual node on the at least one subcircuit, calculating a coupled noise at the victim pin contributed by the at least one subcircuit in response to the power source being applied, comparing the coupled noise to a threshold noise level, and altering the IC design when the coupled noise exceeds the threshold noise level.
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5.发明申请公开(公告)号：US20190362045A1
公开(公告)日：2019-11-28
申请号：US15988125
申请日：2018-05-24
摘要： A system and method to perform an integrated circuit design involves selecting a net among a plurality of nets of the integrated circuit design as a victim net. Each net connects a pair of nodes of the integrated circuit design and each node represents a logic element of the integrated circuit design. The method also includes determining aggressor nets among the plurality of nets for the victim net and determining a corresponding weight value for each of the aggressor nets and, for each of the aggressor nets, multiplying the coupled noise originating from the aggressor net with the corresponding weight value to obtain a weighted coupled noise value. A cumulative coupled noise value is obtained for the victim net as a sum of the weighted coupled noise values associated with each of the aggressor nets. A result of the integrated circuit design is provided for fabrication into an integrated circuit.
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6.发明申请公开(公告)号：US20190005182A1
公开(公告)日：2019-01-03
申请号：US16126590
申请日：2018-09-10
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5009 , G06F17/5036 , G06F17/5077
摘要： A method, system, and computer product for performing a coupled noise analysis in an integrated circuit (IC) design include copying one or more victim circuit sections of a victim circuit in the IC, generating a blockage circuit section that represents a blockage aggressor circuit in the IC, using the copied one or more victim sections of the victim circuit, determining at least one subcircuit from the blockage circuit section, selecting, for a victim pin on the victim circuit, a power-driven virtual node on the at least one subcircuit, applying a power source to the power-driven virtual node on the at least one subcircuit, calculating a coupled noise at the victim pin contributed by the at least one subcircuit in response to the power source being applied, comparing the coupled noise to a threshold noise level, and altering the IC design when the coupled noise exceeds the threshold noise level.
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7.发明授权公开(公告)号：US11017137B2
公开(公告)日：2021-05-25
申请号：US16595451
申请日：2019-10-07
发明人： Chaitanya Ravindra Peddawad , Jeffrey Hemmett , Jason D. Morsey , Steven E. Washburn , Peter Elmendorf , Debjit Sinha , Kerim Kalafala
IPC分类号： G06F30/33 , G06F30/327 , G06F30/392 , G06F119/12
摘要： The efficiency of electronic design automation is increased by building, as an electronic data structure, a timing graph characterizing a putative integrated circuit design; identifying at least one of an edge and a node in the timing graph that requires canonical timing adjustment; and electronically calculating a deterministic timing adjustment for each of a plurality of corner cases. Based on the calculated deterministic timing adjustment for each of the plurality of corner cases, the canonical timing adjustment is determined for the at least one of an edge and a node; the canonical timing adjustment is applied to the timing graph; and the timing graph is updated based on the application of the canonical timing adjustment.
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公开(公告)号：US10552570B2
公开(公告)日：2020-02-04
申请号：US16126590
申请日：2018-09-10
IPC分类号： G06F17/50
摘要： A method, system, and computer product for performing a coupled noise analysis in an integrated circuit (IC) design include copying one or more victim circuit sections of a victim circuit in the IC, generating a blockage circuit section that represents a blockage aggressor circuit in the IC, using the copied one or more victim circuit sections of the victim circuit, determining at least one subcircuit from the blockage circuit section, selecting, for a victim pin on the victim circuit, a power-driven virtual node on the at least one subcircuit, applying a power source to the power-driven virtual node on the at least one subcircuit, calculating a coupled noise at the victim pin contributed by the at least one subcircuit in response to the power source being applied, comparing the coupled noise to a threshold noise level, and altering the IC design when the coupled noise exceeds the threshold noise level.
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公开(公告)号：US10169514B2
公开(公告)日：2019-01-01
申请号：US15408856
申请日：2017-01-18
IPC分类号： G06F17/50
摘要： A system to design an integrated circuit and a method of fabricating an integrated circuit include performing a design change for a net among a plurality of nets of the integrated circuit. An extraction is performed for the net and includes re-computing values for a resistor-capacitor (RC) circuit representation of the net. Re-computed values resulting from the re-computing and a timestamp of the extraction are recorded. A capacitance value of a capacitor coupling the net with a neighboring net in the RC circuit representation of the neighboring net is changed to be the capacitance value of the capacitor coupling the net with the neighboring net that was re-computed for the RC circuit representation of the net. Timing and noise parameters are for the net and the neighboring net are updated to updated timing and noise parameters, and timing analysis is performed based on the updated timing and noise parameters.
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10.发明申请公开(公告)号：US20180203969A1
公开(公告)日：2018-07-19
申请号：US15408856
申请日：2017-01-18
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5031 , G06F17/5036 , G06F17/5081 , G06F2217/82 , G06F2217/84
摘要： A system to design an integrated circuit and a method of fabricating an integrated circuit include performing a design change for a net among a plurality of nets of the integrated circuit. An extraction is performed for the net and includes re-computing values for a resistor-capacitor (RC) circuit representation of the net. Re-computed values resulting from the re-computing and a timestamp of the extraction are recorded. A capacitance value of a capacitor coupling the net with a neighboring net in the RC circuit representation of the neighboring net is changed to be the capacitance value of the capacitor coupling the net with the neighboring net that was re-computed for the RC circuit representation of the net. Timing and noise parameters are for the net and the neighboring net are updated to updated timing and noise parameters, and timing analysis is performed based on the updated timing and noise parameters.
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