A system and method of performing variable accuracy incremental timing analysis in integrated circuit development includes generating a timing graph for interconnected components. The timing graph represents each pin as a node and each interconnection as an arc. A first node or arc is selected. First-level timing values are obtained for the first node or arc using a first timing model that provides a first level of accuracy. n timing models with corresponding n levels of accuracy are pre-selected. The first-level timing values are copied as second-level timing values and as timing values for every other one of the n levels of accuracy for the first node or arc. A second node or arc downstream from the first node or arc is selected. Second-level timing values for the second node or arc are obtained using a second timing model that provides a second level of accuracy.