公开(公告)号：US11245075B2

公开(公告)日：2022-02-08

申请号：US16882704

申请日：2020-05-25

Applicant: International Business Machines Corporation

Inventor： Sri Sri-Jayantha ,  Vijayeshwar Khanna ,  Arun Sharma ,  Hien Dang

IPC: H01L51/00

Abstract: An organic substrate and method of making with optimal thermal warp characteristics is disclosed. The organic substrate has one or more top layers and one or more bottom layers. A chip footprint region is a surface region on each of the top and bottom layers that is defined as the projection of one or more semiconductor chips (chips) on the surface of each of the top and bottom layers. One or more top removal patterns are located on and may or may not remove material from the surface of one or more of the top layers within the chip footprint region of the respective top layer. One or more bottom removal patterns are located on and remove material from the surface of one or more of the bottom layers outside the chip footprint region of the respective bottom layer. The removal of the material from one or more of the top layers and/or bottom layers changes and optimizes a thermal warp of the organic substrate. In some embodiments, a Shape Inversion Temperature (SIT) of the substrate is made equal to or above a reflow temperature.

公开(公告)号：US20140151849A1

公开(公告)日：2014-06-05

申请号：US14157755

申请日：2014-01-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： David Questad ,  Vijayeshwar D. Khanna ,  Jennifer V. Muncy ,  Arun Sharma ,  Sri M. Sri-Jayantha ,  Lorenzo Valdevit

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0231 ,  H05K1/0271 ,  H05K1/111 ,  H05K3/3436 ,  H05K3/3442 ,  H05K2201/09036 ,  H05K2201/10015 ,  H05K2201/10727 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T428/24479 ,  H01L2224/0401 ,  H01L2924/00

Abstract: An electronic module includes a substrate including at least one structure that reduces stress flow through the substrate, wherein the structure includes at least one trench in a surface of the substrate, and a plurality of capacitor legs disposed on an upper surface of the substrate.

Abstract translation: 一种电子模块包括一个包括至少一个结构的衬底，该结构减少了通过衬底的应力流动，其中该结构包括衬底的表面中的至少一个沟槽和设置在衬底的上表面上的多个电容器脚。

公开(公告)号：US20210367152A1

公开(公告)日：2021-11-25

申请号：US16882704

申请日：2020-05-25

Applicant: International Business Machines Corporation

Inventor： Sri Sri-Jayantha ,  Vijayeshwar Khanna ,  Arun Sharma ,  Hien Dang

IPC: H01L51/00

Abstract: An organic substrate and method of making with optimal thermal warp characteristics is disclosed. The organic substrate has one or more top layers and one or more bottom layers. A chip footprint region is a surface region on each of the top and bottom layers that is defined as the projection of one or more semiconductor chips (chips) on the surface of each of the top and bottom layers. One or more top removal patterns are located on and may or may not remove material from the surface of one or more of the top layers within the chip footprint region of the respective top layer. One or more bottom removal patterns are located on and remove material from the surface of one or more of the bottom layers outside the chip footprint region of the respective bottom layer. The removal of the material from one or more of the top layers and/or bottom layers changes and optimizes a thermal warp of the organic substrate. In some embodiments, a Shape Inversion Temperature (SIT) of the substrate is made equal to or above a reflow temperature.

公开(公告)号：US08987031B2

公开(公告)日：2015-03-24

申请号：US13886646

申请日：2013-05-03

Applicant: International Business Machines Corporation

Inventor： Michael S. Gordon ,  Christopher V. Jahnes ,  Eric A. Joseph ,  Hiroyuki Miyazoe ,  Kenneth P. Rodbell ,  Arun Sharma ,  Sri M. Sri-Jayantha

IPC: H01L21/00 ,  H01L31/18 ,  G01T1/04

CPC classification number: H01L31/18 ,  G01T1/04 ,  G01T1/18 ,  H01J47/062 ,  H01J47/08

Abstract: A method for a constructing radiation detector includes fabricating a multi-layer structure upon a wafer, the multi-layer structure comprising a plurality of metal layers, a plurality of sacrificial layers, and a plurality of insulating layers, forming a cavity within the multi-layer structure, filling the cavity with a gas that ionizes in response to nuclear radiation, and sealing the gas within the cavity.

Abstract translation: 一种用于构造辐射探测器的方法包括在晶片上制造多层结构，所述多层结构包括多个金属层，多个牺牲层和多个绝缘层， 层结构，用响应于核辐射电离的气体填充空腔，并将气体密封在空腔内。

公开(公告)号：US20140329351A1

公开(公告)日：2014-11-06

申请号：US13886646

申请日：2013-05-03

Applicant: International Business Machines Corporation

Inventor： MICHAEL S. GORDON ,  Christopher V. Jahnes ,  Eric A. Joseph ,  Hiroyuki Miyazoe ,  Kenneth P. Rodbell ,  Arun Sharma ,  Sri M. Sri-Jayantha

IPC: H01L31/18

CPC classification number: H01L31/18 ,  G01T1/04 ,  G01T1/18 ,  H01J47/062 ,  H01J47/08

Abstract: A method for a constructing radiation detector includes fabricating a multi-layer structure upon a wafer, the multi-layer structure comprising a plurality of metal layers, a plurality of sacrificial layers, and a plurality of insulating layers, forming a cavity within the multi-layer structure, filling the cavity with a gas that ionizes in response to nuclear radiation, and sealing the gas within the cavity.

Abstract translation: 一种用于构造辐射探测器的方法包括在晶片上制造多层结构，所述多层结构包括多个金属层，多个牺牲层和多个绝缘层， 层结构，用响应于核辐射电离的气体填充空腔，并将气体密封在空腔内。