公开(公告)号：US20020054583A1

公开(公告)日：2002-05-09

申请号：US09974273

申请日：2001-10-10

Applicant: InterDigital Technology Corporation

Inventor： Robert L. Olesen ,  Timothy A. Axness ,  Leonid Kazakevich

IPC: H04L012/26

CPC classification number: H04W52/52 ,  H03G3/3078 ,  H03M1/185 ,  H04B17/318 ,  H04L5/1484

Abstract: A method and system for automatic gain control (AGC) in a TDD communication system, wherein each time slot of the communication signal contains a preamble in binary phase shift keying (BPSK) format, located at the beginning of the time slot. The channel estimation by the receiver is improved since the preamble allows AGC to quickly estimate the signal strength and adjust the gain accordingly. This permits all data symbols within the data burst, which follows the preamble, to be correctly received, and results in a midamble channel estimate that is much more accurate. It also allows the AGC circuit within the TDD receiver to be greatly simplified.

Abstract translation: 一种用于TDD通信系统中的自动增益控制（AGC）的方法和系统，其中通信信号的每个时隙包含位于时隙开头的二进制相移键控（BPSK）格式的前导码。 由于前同步码允许AGC快速估计信号强度并相应地调整增益，所以改善了接收机的信道估计。 这允许正确地接收跟随前导码的数据突发内的所有数据符号，并且导致更准确的中间码信道估计。 它还允许TDD接收机内的AGC电路大大简化。

公开(公告)号：US20040072547A1

公开(公告)日：2004-04-15

申请号：US10456300

申请日：2003-06-06

Applicant: InterDigital Technology Corporation

Inventor： Timothy A. Axness ,  Leonid Kazakevich

IPC: H04B001/00

CPC classification number: H04L5/06 ,  H03G3/3052 ,  H04B1/30 ,  H04L27/2608 ,  H04L27/3845

Abstract: A radio communications device such as a receiver, transmitter or transceiver provides direct conversion of quadrature signals between a radio frequency signal and a plurality of resolved channels. The device provides block processing of multiple RF carriers in a wireless communication system using a direct conversion transmitter/receiver and baseband signal processing.

Abstract translation: 诸如接收机，发射机或收发机之类的无线电通信设备在射频信号和多个解决的信道之间提供正交信号的直接转换。 该设备使用直接转换发射机/接收机和基带信号处理在无线通信系统中提供多个RF载波的块处理。

公开(公告)号：US20030105895A1

公开(公告)日：2003-06-05

申请号：US10080899

申请日：2002-02-22

Applicant: InterDigital Technology Corporation

Inventor： Joseph Gredone ,  Alfred Stufflet ,  Timothy A. Axness

IPC: G06F013/00

CPC classification number: H04L25/14 ,  H03M9/00

Abstract: A hybrid serial/parallel bus interface for a user equipment (UE) has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block.

Abstract translation: 用于用户设备（UE）的混合串行/并行总线接口具有数据块解复用装置。 数据块解复用装置具有被配置为接收数据块并将数据块解复用为多个半字节的输入。 对于每个半字节，并行到串行转换器将半字节转换为串行数据。 一行传输每个半字节的串行数据。 串行到并行转换器转换每个半字节的串行数据以恢复该半字节。 数据块重建装置将恢复的半字节组合到数据块中。

公开(公告)号：US20030105894A1

公开(公告)日：2003-06-05

申请号：US10080817

申请日：2002-02-22

Applicant: InterDigital Technology Corporation

Inventor： Joseph Gredone ,  Alfred Stufflet ,  Timothy A. Axness

IPC: G06F013/00

CPC classification number: H04L25/14 ,  H03M9/00

Abstract: A hybrid serial/parallel bus interface method for a base station has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block.

Abstract translation: 用于基站的混合串行/并行总线接口方法具有数据块解复用装置。 数据块解复用装置具有被配置为接收数据块并将数据块解复用为多个半字节的输入。 对于每个半字节，并行到串行转换器将半字节转换为串行数据。 一行传输每个半字节的串行数据。 串行到并行转换器转换每个半字节的串行数据以恢复该半字节。 数据块重建装置将恢复的半字节组合到数据块中。

公开(公告)号：US20030105896A1

公开(公告)日：2003-06-05

申请号：US10081466

申请日：2002-02-22

Applicant: InterDigital Technology Corporation

Inventor： Joseph Gredone ,  Alfred Stufflet ,  Timothy A. Axness

IPC: G06F013/00

CPC classification number: H04L25/14 ,  H03M9/00

Abstract: A hybrid serial/parallel bus interface for a base station has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block.

Abstract translation: 用于基站的混合串行/并行总线接口具有数据块解复用装置。 数据块解复用装置具有被配置为接收数据块并将数据块解复用为多个半字节的输入。 对于每个半字节，并行到串行转换器将半字节转换为串行数据。 一行传输每个半字节的串行数据。 串行到并行转换器转换每个半字节的串行数据以恢复该半字节。 数据块重建装置将恢复的半字节组合到数据块中。

公开(公告)号：US20030105893A1

公开(公告)日：2003-06-05

申请号：US10080480

申请日：2002-02-22

Applicant: InterDigital Technology Corporation

Inventor： Joseph Gredone ,  Alfred Stufflet ,  Timothy A. Axness

IPC: G06F013/00

CPC classification number: H04L25/14 ,  H03M9/00

Abstract: A hybrid serial/parallel bus interface method for a user equipment (UE) has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block.

Abstract translation: 用于用户设备（UE）的混合串行/并行总线接口方法具有数据块解复用器件。 数据块解复用装置具有被配置为接收数据块并将数据块解复用为多个半字节的输入。 对于每个半字节，并行到串行转换器将半字节转换为串行数据。 一行传输每个半字节的串行数据。 串行到并行转换器转换每个半字节的串行数据以恢复该半字节。 数据块重建装置将恢复的半字节组合到数据块中。

公开(公告)号：US20040242172A1

公开(公告)日：2004-12-02

申请号：US10799951

申请日：2004-03-12

Applicant: InterDigital Technology Corporation

Inventor： John W. Haim ,  Fryderyk Tyra ,  Louis J. Guccione ,  Timothy A. Axness ,  Donald M. Grieco

IPC: H03G003/20

CPC classification number: H04W52/52 ,  H03G3/001 ,  H03G3/3052 ,  H03G3/3078

Abstract: An automatic gain control (AGC) method according to the present invention applies an initial gain by a digital AGC circuit in a timeslot is determined using a final calculated gain from the same timeslot in the previous frame together with an offset factor. An erase function is activated for a given data sample block when the number of saturated data samples that are detected within the block exceeds a threshold value. The power measurement made by the AGC circuit and used to update the gain is adjusted based on the number of measured data samples that are saturated. These elements provide a gain limiting function and allows limiting of the dynamic range for further signal processing

Abstract translation: 根据本发明的自动增益控制（AGC）方法，利用来自前一帧中的相同时隙的最终计算的增益以及偏移因子来确定时隙中的数字AGC电路的初始增益。 当在该块内检测到的饱和数据样本的数量超过阈值时，对于给定的数据采样块，擦除功能被激活。 由AGC电路进行的用于更新增益的功率测量基于饱和的测量数据样本的数量进行调整。 这些元件提供增益限制功能，并允许限制用于进一步信号处理的动态范围

公开(公告)号：US20030202571A1

公开(公告)日：2003-10-30

申请号：US10322166

申请日：2002-12-18

Applicant: InterDigital Technology Corporation

Inventor： Kenneth P. Kearney ,  Leonid Kazakevich ,  Timothy A. Axness ,  James Nolan

IPC: H04Q001/20 ,  H04B003/46

CPC classification number: H04B17/0087 ,  H04B17/391

Abstract: A method for emulating signal impairments to enable dynamic evaluation of transmit and receive modem performance through the use of computer-generated models enabling both an evaluation of system performance as well as a comparison of results obtained from system designs respectively exposed to both impaired and unimpaired conditions to enable direct comparison as well as comparison with standardized measurement values to facilitate system design activities prior to any hardware implementation.

Abstract translation: 一种用于模拟信号损伤的方法，以通过使用计算机生成的模型来动态评估发送和接收调制解调器的性能，从而能够对系统性能进行评估，并对从分别暴露于受损和未受损条件的系统设计获得的结果进行比较 以实现直接比较以及与标准测量值的比较，以便在任何硬件实施之前促进系统设计活动。

公开(公告)号：US20030095057A1

公开(公告)日：2003-05-22

申请号：US09990060

申请日：2001-11-21

Applicant: InterDigital Technology Corporation

Inventor： Joseph Gredone ,  Alfred Stufflet ,  Timothy A. Axness

IPC: H03M009/00

CPC classification number: H04L25/14 ,  H03M9/00

Abstract: A hybrid serial/parallel bus interface has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block.

Abstract translation: 混合串行/并行总线接口具有数据块解复用装置。 数据块解复用装置具有被配置为接收数据块并将数据块解复用为多个半字节的输入。 对于每个半字节，并行到串行转换器将半字节转换为串行数据。 一行传输每个半字节的串行数据。 串行到并行转换器转换每个半字节的串行数据以恢复该半字节。 数据块重建装置将恢复的半字节组合到数据块中。