公开(公告)号：US20030099217A1

公开(公告)日：2003-05-29

申请号：US10123613

申请日：2002-04-16

Applicant: InterDigital Technology Corporation

Inventor： Douglas R. Castor ,  George W. McClellan ,  Joseph T. Morabito

IPC: H04B007/216

CPC classification number: H04L1/0059 ,  H03M13/09 ,  H03M13/23 ,  H03M13/271 ,  H03M13/276 ,  H03M13/2957 ,  H03M13/6362 ,  H03M13/6513 ,  H04L1/0045 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

Abstract: The invention includes various embodiments for use in physical layer processing. One embodiment determines the address mapping of bits in the physical channel buffer from the address of bits in the first interleaver buffer. The physical channel buffer addresses are determined corresponding to addresses of the bits after rate matching, bit scrambling, second interleaving and physical channel mapping. The bits are directly read from the first interleaver buffer and written to the physical channel buffer using the determined physical channel buffer addresses. Another embodiment determines the address mapping of bits in the first interleaver buffer from the address of bits in the physical channel buffer. The first interleaver buffer addresses are determined corresponding to addresses of the bits after reverse rate matching, reverse bit scrambling, reverse second interleaving and reverse physical channel mapping. The bits are directly read from the determined first interleaver buffer addresses and written to the physical channel buffer addresses.

公开(公告)号：US20040014447A1

公开(公告)日：2004-01-22

申请号：US10414125

申请日：2003-04-15

Applicant: InterDigital Technology Corporation

Inventor： Edward L. Hepler ,  Michael F. Starsinic ,  David S. Bass ,  Binish Desai ,  Alan M. Levi ,  George W. McClellan ,  Douglas R. Castor

IPC: H04B001/06

CPC classification number: H04W88/06 ,  H04B1/0067 ,  H04B1/406 ,  H04B1/707 ,  H04B7/2618 ,  H04B2201/70707 ,  H04L1/0061 ,  H04L1/0068 ,  H04L1/0071 ,  H04L1/08 ,  H04L2001/0094 ,  H04W28/18 ,  H04W74/02 ,  H04W80/00

Abstract: A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block, a composite channel processing block and a chip rate processing block. At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.

Abstract translation: 一种在无线通信系统中使用的物理层传输复合处理系统。 提供多个互连的处理块。 块通过读数据总线，写数据总线和控制总线相互连接。 这些块包括传输信道处理块，复合信道处理块和码片速率处理块。 至少两个块能够处理多种无线格式的数据。 对于特定的无线模式，第一组参数被编程到块中。 操作块以特定的无线格式模式处理数据。

公开(公告)号：US20030186684A1

公开(公告)日：2003-10-02

申请号：US10400878

申请日：2003-03-27

Applicant: InterDigital Technology Corporation

Inventor： Kenneth P. Kearney ,  George W. McClellan ,  Ryan E. Drummond ,  Alan M. Levi

IPC: H04M001/66

CPC classification number: H04W68/025 ,  H04W52/0216 ,  H04W68/00 ,  H04W68/02 ,  H04W80/00 ,  H04W88/02 ,  Y02D70/1242 ,  Y02D70/1262 ,  Y02D70/24

Abstract: A wireless communication system implements wireless communications between a base station and a plurality of User Equipments (UEs) including paging of UEs by initially processing paging indicator information. A first embodiment involves a UE's physical layer L1 being configured for interpreting a paging indicator (PI) to activate a preset decoding configuration to process paging data in a pre-specified paging channel (PCH). A second embodiment involves the physical layer control of a next higher level, L2, interpreting the paging indicator and configuring the physical layer L1 to process paging data in a pre-specified PCH.

Abstract translation: 无线通信系统通过初始处理寻呼指示符信息来实现基站和多个用户设备（UE）之间的无线通信，包括UE的寻呼。 第一实施例涉及UE的物理层L1被配置用于解释寻呼指示符（PI）以激活预设解码配置以处理预先指定的寻呼信道（PCH）中的寻呼数据。 第二实施例涉及下一较高级别的物理层控制L2，解释寻呼指示符并配置物理层L1以处理预先指定的PCH中的寻呼数据。