公开(公告)号：US20040014447A1

公开(公告)日：2004-01-22

申请号：US10414125

申请日：2003-04-15

Applicant: InterDigital Technology Corporation

Inventor： Edward L. Hepler ,  Michael F. Starsinic ,  David S. Bass ,  Binish Desai ,  Alan M. Levi ,  George W. McClellan ,  Douglas R. Castor

IPC: H04B001/06

CPC classification number: H04W88/06 ,  H04B1/0067 ,  H04B1/406 ,  H04B1/707 ,  H04B7/2618 ,  H04B2201/70707 ,  H04L1/0061 ,  H04L1/0068 ,  H04L1/0071 ,  H04L1/08 ,  H04L2001/0094 ,  H04W28/18 ,  H04W74/02 ,  H04W80/00

Abstract: A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block, a composite channel processing block and a chip rate processing block. At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.

Abstract translation: 一种在无线通信系统中使用的物理层传输复合处理系统。 提供多个互连的处理块。 块通过读数据总线，写数据总线和控制总线相互连接。 这些块包括传输信道处理块，复合信道处理块和码片速率处理块。 至少两个块能够处理多种无线格式的数据。 对于特定的无线模式，第一组参数被编程到块中。 操作块以特定的无线格式模式处理数据。

公开(公告)号：US20030066019A1

公开(公告)日：2003-04-03

申请号：US10037609

申请日：2002-01-02

Applicant: InterDigital Technology Corporation

Inventor： Edward L. Hepler ,  Michael F. Starsinic

IPC: G06F007/52 ,  H03M013/03

CPC classification number: H03M13/3905 ,  H03M13/3972 ,  H03M13/6505

Abstract: The sliding window approach to pipeline maximum a posteriori (MAP) decoder architecture is modified to decrease processing time. Once the forward metrics have been calculated for the first sliding window of the decoder, the reverse metrics for each window are calculated while the forward metrics for the next window are calculated. As each new forward metric is calculated and stored into memory, the forward metric from the previous window is read from memory for use with reverse metric being calculated in calculating extrinsic value. Each forward metric for use in calculating an extrinsic value is read from memory on the same clock edge that the new forward metric is written to the same memory location. Although this architecture was developed for a turbo decoder, all convolution codes can use the MAP algorithm of the present invention.

Abstract translation: 流水线最大后验（MAP）解码器架构的滑动窗口方法被修改以减少处理时间。 一旦为解码器的第一滑动窗口计算了前向量度，则在计算下一个窗口的前向量度时，计算每个窗口的反向度量。 当每个新的前向度量被计算并存储到存储器中时，从存储器中读取来自前一窗口的前向度量用于在计算外在值时计算的反向度量。 用于计算外在值的每个前向量度在相同的时钟边沿从存储器读取，该时钟边沿将新的前向量度写入相同的存储器位置。 虽然该架构是为turbo解码器开发的，但是所有的卷积码都可以使用本发明的MAP算法。