公开(公告)号：US10102129B2

公开(公告)日：2018-10-16

申请号：US14976678

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Krishna N. Vinod ,  Avinash Sodani ,  Zainulabedin J. Aurangabadwala

IPC: G06F12/08 ,  G06F12/0815 ,  G06F12/0811

Abstract: A processor includes a processing core, a L1 cache comprising a first processing core and a first L1 cache comprising a first L1 cache data entry of a plurality of L1 cache data entries to store data. The processor also includes an L2 cache comprising a first L2 cache data entry of a plurality of L2 cache data entries. The first L2 cache data entry corresponds to the first L1 cache data entry and each of the plurality of L2 cache data entries are associated with a corresponding presence bit (pbit) of a plurality of pbits. Each of the plurality of pbits indicates a status of a corresponding one of the plurality of L2 cache data entries. The processor also includes a cache controller, which in response to a first request among a plurality of requests to access the data at the first L1 cache data entry, determines that a copy of the data is stored in the first L2 cache data entry; and retrieves the copy of the data from the L2 cache data entry in view of the status of the pbit.

公开(公告)号：US20170177483A1

公开(公告)日：2017-06-22

申请号：US14976678

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Krishna N. Vinod ,  Avinash Sodani ,  Zainulabedin J. Aurangabadwala

IPC: G06F12/08

CPC classification number: G06F12/0815 ,  G06F12/0811 ,  G06F2212/621

Abstract: A processor includes a processing core, a L1 cache comprising a first processing core and a first L1 cache comprising a first L1 cache data entry of a plurality of L1 cache data entries to store data. The processor also includes an L2 cache comprising a first L2 cache data entry of a plurality of L2 cache data entries. The first L2 cache data entry corresponds to the first L1 cache data entry and each of the plurality of L2 cache data entries are associated with a corresponding presence bit (pbit) of a plurality of pbits. Each of the plurality of pbits indicates a status of a corresponding one of the plurality of L2 cache data entries. The processor also includes a cache controller, which in response to a first request among a plurality of requests to access the data at the first L1 cache data entry, determines that a copy of the data is stored in the first L2 cache data entry; and retrieves the copy of the data from the L2 cache data entry in view of the status of the pbit.