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公开(公告)号：US20220078911A1
公开(公告)日：2022-03-10
申请号：US17090911
申请日：2020-11-06
Applicant: Intel Corporation
Inventor： Tin Poay CHUAH , Min Suet LIM , Chee Chun YEE , Yew San LIM , Eng Huat GOH
Abstract: A multilayer printed circuit board including a first printed circuit board portion, including a first inserting connector, including a plurality of contacts for creating a first removable bus connection; a second printed circuit board portion, including a second inserting connector, including a plurality of contacts for creating a second removable bus connection; a third printed circuit board portion, connected between the first printed circuit board portion and to the second printed circuit board portion, wherein a rigidity of the third printed circuit board portion is less than a rigidity of each of the first printed circuit board portion and the second printed circuit board portion; wherein the multilayer printed circuit board is foldable along the third printed circuit board portion and, if so folded, the first printed circuit board portion is arranged on top of the second printed circuit board portion.
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公开(公告)号：US20220075410A1
公开(公告)日：2022-03-10
申请号：US17089752
申请日：2020-11-05
Applicant: Intel Corporation
Inventor： Min Suet LIM , Chee Chun YEE , Yew San LIM , Jeff KU , Tin Poay CHUAH
Abstract: According to the present disclosure, a laptop may be provided with a smaller z-height using a motherboard assembly, including a motherboard having a plurality of components coupled thereon, a thermal transfer unit coupled to one or more component on the motherboard and attachment members for holding the motherboard in a lower compartment of a laptop clamshell casing at an inclining position.
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公开(公告)号：US20220068834A1
公开(公告)日：2022-03-03
申请号：US17089756
申请日：2020-11-05
Applicant: Intel Corporation
Inventor： Eng Huat GOH , Tin Poay CHUAH , Yew San LIM , Min Suet LIM
IPC: H01L23/552 , H05K1/02 , H05K3/28
Abstract: According to the various aspects, the present device includes a printed circuit board having a top surface and a bottom surface, with a plurality of semiconductor devices coupled to the top surface and a flexible electromagnetic shield wrap conformally positioned over and between the plurality of semiconductor devices and the top surface of the printed circuit board. The flexible electromagnetic shield wrap is conformally positioned by applying a vacuum and is removable after the vacuum seal is broken.
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公开(公告)号：US20220066509A1
公开(公告)日：2022-03-03
申请号：US17088620
申请日：2020-11-04
Applicant: Intel Corporation
Inventor： Chee Chun YEE , Tin Poay CHUAH , Yew San LIM , Min Suet LIM , Jeff KU
IPC: G06F1/16
Abstract: According to the various examples, a dual display system having a first panel having a first display area, a second panel having a second display area, and a connector assembly, attached to the first and second panels, that is configured to enable the first and second panels to rotate around three-directional axes. The connector assembly includes an elongated member and a hinge assembly, which are configured for attachment to the first and second display panels. The present dual display system may have several functional modalities, including use as a desktop computer, a laptop computer, a tablet, and a panoramic display.
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5.发明公开公开(公告)号：US20230397323A1
公开(公告)日：2023-12-07
申请号：US17834641
申请日：2022-06-07
Applicant: Intel Corporation
Inventor： Min Suet LIM , Tin Poay CHUAH , Yew San LIM , Jeff KU , Twan Sing LOO , Poh Boon KHOO , Jiun Hann SIR
IPC: H05K1/02 , H01L23/367 , H01L25/065 , H01L25/18 , H05K3/22 , H01L23/42
CPC classification number: H05K1/0204 , H01L23/3675 , H01L25/0652 , H01L25/18 , H05K3/22 , H01L23/42 , H01L2224/32225 , H01L24/32
Abstract: Embodiments disclosed herein include a printed circuit board (PCB). In an embodiment, the PCB comprises a substrate with a first surface and a second surface opposite from the first surface. In an embodiment, a first slot is through a thickness of the substrate, and a second slot is through the thickness of the substrate, where the first slot is parallel to the second slot. In an embodiment, a metal plate is provided on the PCB. In an embodiment the metal plate comprises a first portion over the first surface of the substrate between the first slot and the second slot, a second portion connected to the first portion, wherein the second portion is in the first slot, and a third portion connected to the first portion, wherein the third portion is in the second slot.
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Patent Agency Ranking
公开(公告)号：US20230123645A1
公开(公告)日：2023-04-20
申请号：US17500983
申请日：2021-10-14
Applicant: Intel Corporation
Inventor： Tin Poay CHUAH , Jeff KU , Yew San LIM , Boon Ping KOH , Min Suet LIM
IPC: H01R12/78 , H01R13/28 , H01R13/629 , H01R13/20 , H01R43/02
Abstract: There may be provided a fastener arrangement. The fastener arrangement may include a first fastener tape including a first plurality of electrically conductive coupling elements and a first plurality of non-electrically conductive coupling elements. The fastener arrangement may further include a second fastener tape comprising a second plurality of electrically conductive coupling elements and a second plurality of non-electrically conductive coupling element. The fastener arrangement may further include a slider couplable to the first fastener tape and the second fastener tape for reversibly interleaving and interlocking the first plurality of electrically conductive and non-electrically conductive coupling elements with their corresponding second plurality of electrically conductive and non-electrically conductive elements. The interleaved and interlocked first and second plurality of electrically conductive coupling elements may form a plurality of conductive-bridges and the interleaved and interlocked first and second plurality of non-electrically conductive coupling elements may form a plurality of insulation-bridges.
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公开(公告)号：US20190394871A1
公开(公告)日：2019-12-26
申请号：US16481043
申请日：2017-03-30
Applicant: Intel Corporation
Inventor： Jia Yan GO , Min Suet LIM , Tin Poay CHUAH , Seok Ling LIM , Howe Yin LOO
IPC: H05K1/02 , H01L23/552 , H01L25/16 , H01L23/498 , H01L21/50 , H05K1/18 , H05K1/11 , H05K3/30
Abstract: Semiconductor packages and a method of forming a semiconductor package are described. The semiconductor package has a foundation layer mounted on a motherboard. The semiconductor package also includes a hole in motherboard (HiMB) that is formed in the motherboard. The semiconductor package has one or more capacitors mounted on an electrical shield. The electrical shield may be embedded in the HiMB of the motherboard. Accordingly, the semiconductor package has capacitors vertically embedded between the electrical shield and the HiMB of the motherboard. The semiconductor package may also have one or more HiMB sidewalls formed on the HiMB, where each of the one or more HiMB sidewalls includes at least one or more plated through holes (PTHs) with an exposed layer. The PTHs may be electrically coupled to the capacitors as the capacitors are vertically embedded between the electrical shield sidewalls and the HiMB sidewalls (i.e., three-dimensional (3D) capacitors).
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8.发明申请公开(公告)号：US20190131227A1
公开(公告)日：2019-05-02
申请号：US16095916
申请日：2016-07-01
Applicant: Intel Corporation
Inventor： Howe Yin LOO , Sujit SHARAN , Tin Poay CHUAH , Ananth PRABHAKUMAR
IPC: H01L23/498 , H01L23/13 , H01L23/14 , H01L23/31 , H01L21/48 , H01L21/768 , H05K1/18
Abstract: Techniques and mechanisms to facilitate connectivity between circuit components via a substrate. In an embodiment, a microelectronic device includes a substrate, wherein a recess region extends from the first side of the substrate and only partially toward a second side of the substrate. First input/output (IO) contacts of a first hardware interface are disposed in the recess region. The first IO contacts are variously coupled to each to a respective metallization layer of the substrate, wherein the recess region extends though one or more other metallization layers of the substrate. In another embodiment, the microelectronic device further comprises second IO contacts of a second hardware interface, the second IO contacts to couple the microelectronic device to a printed circuit board.
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公开(公告)号：US20240147654A1
公开(公告)日：2024-05-02
申请号：US18050502
申请日：2022-10-28
Applicant: Intel Corporation
Inventor： Jiunn Shyong CHEE , Howe Yin LOO , Tin Poay CHUAH , Chin Kung GOH , Yew San LIM
CPC classification number: H05K7/20136 , G06F1/203
Abstract: The present disclosure is directed to a laptop arrangement including: a chassis defining a space that is divided into a first compartment and a second compartment, the first compartment including an air inlet and the second compartment including an air outlet; and a partitioning element positioned between the first and second compartments, whereby the partitioning element at least partially seals the first compartment from the second compartment and enables the second compartment to have a greater pressurization than the first compartment.
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公开(公告)号：US20240006786A1
公开(公告)日：2024-01-04
申请号：US17857051
申请日：2022-07-04
Applicant: Intel Corporation
Inventor： Howe Yin LOO , Tin Poay CHUAH , Jenny Shio Yin ONG , Chee Min LOH , Bok Eng CHEAH , Jackson Chung Peng KONG , Seok Ling LIM , Kooi Chi OOI
CPC classification number: H01R12/57 , H01R12/7082 , H01R12/707
Abstract: The present disclosure is directed to a printed circuit board having a composite upper surface with a first section of a first-type of printed circuit board and a second section of a second-type of printed circuit board, for which the first section of the first-type of printed circuit board and the second section of the second-type of printed circuit board are coupled, respectively, to at least one device that is configured to abridge the first and second sections of the composite upper surface. In an aspect, the second-type of printed circuit board is configured to be embedded in the first-type of printed circuit board and the first-type of printed circuit board is configured to receive the second-type of printed circuit board.
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