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公开(公告)号：US12135643B2
公开(公告)日：2024-11-05
申请号：US17096274
申请日：2020-11-12
Applicant: Intel Corporation
Inventor： Michael Kounavis , Siddhartha Chhabra , David M. Durham
IPC: G06F12/0802 , H04L9/32
Abstract: Techniques and mechanisms for metadata, which corresponds to cached data, to be selectively stored to a sequestered memory region. In an embodiment, integrated circuitry evaluates whether a line of a cache can accommodate a first representation of both the data and some corresponding metadata. Where the cache line can accommodate the first representation, said first representation is generated and stored to the line. Otherwise, a second representation of the data is generated and stored to a cache line, and the metadata is stored to a sequestered memory region that is external to the cache. The cache line include an indication as to whether the metadata is represented in the cache line, or is stored in the sequestered memory region. In another embodiment, a metric of utilization of the sequestered memory region is provided to software which determines whether a capacity of the sequestered memory region is to be modified.
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2.发明授权公开(公告)号：US11082432B2
公开(公告)日：2021-08-03
申请号：US15831633
申请日：2017-12-05
Applicant: Intel Corporation
Inventor： Michael Kounavis , Amitabh Das , Sergej Deutsch , Karanvir S. Grewal , David M. Durham
Abstract: Before sending a message to a destination device, a source device automatically uses a pattern matching algorithm to analyze entropy characteristics of a plaintext version of the message. The pattern matching algorithm uses at least one pattern matching test to generate at least one entropy metric for the message. The source device automatically determines whether the message has sufficiently low entropy, based on results of the pattern matching algorithm. In response to a determination that the message does not have sufficiently low entropy, the source device automatically generates integrity metadata for the message and sends the integrity metadata to the destination device. However, in response to a determination that the message has sufficiently low entropy, the source device sends the message to the destination device without sending any integrity metadata for the message to the destination device. Other embodiments are described and claimed.
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公开(公告)号：US10929527B2
公开(公告)日：2021-02-23
申请号：US15848962
申请日：2017-12-20
Applicant: INTEL CORPORATION
Inventor： Michael Kounavis , David Durham , Sergej Deutsch , Saeedeh Komijani , Amitabh Das
Abstract: Logic may implement implicit integrity techniques to maintain integrity of data. Logic may perform operations on data stored in main memory, cache, flash, data storage, or any other memory. Logic may perform more than one pattern check to determine repetitions of entities within the data. Logic may determine entropy index values and/or Boolean values and/or may compare the results to threshold values to determine if a data unit is valid. Logic may merge a tag with the data unit without expanding the data unit to create an encoded data unit. Logic may decode and process the encoded data unit to determine the data unit and the tag. Logic may determine value histograms for two or more entities, determine a sum of repetitions of the two or more entities, and compare the sum to a threshold value. Logic may determine that a data unit is valid or is corrupted.
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公开(公告)号：US20200327072A1
公开(公告)日：2020-10-15
申请号：US16912251
申请日：2020-06-25
Applicant: Intel Corporation
Inventor： Michael Kounavis , Anna Trikalinou
IPC: G06F12/14 , G06F12/1081 , G06F12/0882 , G06F21/79 , H04L9/06 , H04L9/32
Abstract: Methods and apparatus relating to secure-ATS (or secure Address Translation Services) using a version tree for replay protection are described. In an embodiment, memory stores data for a secured device. The stored data comprising information for one or more intermediate nodes and one or more leaf nodes. Logic circuitry allows/disallows access to contents of a memory region associated with a first leaf node from the one or more leaf nodes by a memory access request based at least in part on whether the memory access request is associated with a permission authenticated by the MAC of the first leaf node. Other embodiments are also disclosed and claimed.
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公开(公告)号：US10672401B2
公开(公告)日：2020-06-02
申请号：US15198193
申请日：2016-06-30
Applicant: INTEL CORPORATION
Inventor： Nikhil Pantpratinidhi , Gokcen Cilingir , Michael Deisher , Ohad Falik , Michael Kounavis
Abstract: Systems, apparatus and methods are described including operations for a dual mode GMM (Gaussian Mixture Model) scoring accelerator for both speech and video data.
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Patent Agency Ranking
公开(公告)号：US20190045030A1
公开(公告)日：2019-02-07
申请号：US15839194
申请日：2017-12-12
Applicant: Intel Corporation
Inventor： Michael Kounavis , David M. Durham , Karanvir Grewal , Wenjie Xiong , Sergej Deutsch
Abstract: A method of data nibble-histogram compression can include determining a first amount of space freed by compressing the input data using a first compression technique, determining a second amount of space freed by compressing the input data using a second, different compression technique, compressing the input data using the compression technique of the first and second compression techniques determined to free up more space to create compressed input data, and inserting into the compressed input data, security data including one of a message authentication control (MAC) and an inventory control tag (ICT).
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公开(公告)号：US11895221B2
公开(公告)日：2024-02-06
申请号：US17835543
申请日：2022-06-08
Applicant: INTEL CORPORATION
Inventor： Michael Kounavis
CPC classification number: H04L9/0631 , H04L9/3026 , H04L2209/122
Abstract: In one example, an apparatus for Advanced Encryption Standard (AES) substitutions box (S-box) encryption includes an S-Box logic function and a MixColumns multiplication operation. The S-box logic function takes as input a state and is an 8-bit to 8-bit logic function, and wherein the S-box logic function is minimized such that an S-box round comprises nine not-and (NAND) levels and duplications of a logical product of the minimized S-box logic function are eliminated. The MixColumns multiplication operation comprises a plurality of factors that are exclusive ORed (XOR) with an output of the S-box round to obtain a scaled 16-byte output.
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8.发明授权公开(公告)号：US11657162B2
公开(公告)日：2023-05-23
申请号：US16361397
申请日：2019-03-22
Applicant: Intel Corporation
Inventor： Michael Kounavis , Antonios Papadimitriou , Anindya Sankar Paul , Micah Sheller , Li Chen , Cory Cornelius , Brandon Edwards
CPC classification number: G06F21/60 , G06F21/52 , G06N3/0454 , G06N3/08
Abstract: In one example an apparatus comprises a memory and a processor to create, from a first deep neural network (DNN) model, a first plurality of DNN models, generate a first set of adversarial examples that are misclassified by the first plurality of deep neural network (DNN) models, determine a first set of activation path differentials between the first plurality of adversarial examples, generate, from the first set of activation path differentials, at least one composite adversarial example which incorporates at least one intersecting critical path that is shared between at least two adversarial examples in the first set of adversarial examples, and use the at least one composite adversarial example to generate a set of inputs for a subsequent training iteration of the DNN model. Other examples may be described.
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公开(公告)号：US20220407680A1
公开(公告)日：2022-12-22
申请号：US17835543
申请日：2022-06-08
Applicant: INTEL CORPORATION
Inventor： Michael Kounavis
Abstract: In one example, an apparatus for Advanced Encryption Standard (AES) substitutions box (S-box) encryption includes an S-Box logic function and a MixColumns multiplication operation. The S-box logic function takes as input a state and is an 8-bit to 8-bit logic function, and wherein the S-box logic function is minimized such that an S-box round comprises nine not-and (NAND) levels and duplications of a logical product of the minimized S-box logic function are eliminated. The MixColumns multiplication operation comprises a plurality of factors that are exclusive ORed (XOR) with an output of the S-box round to obtain a scaled 16-byte output.
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10.发明申请公开(公告)号：US20200026661A1
公开(公告)日：2020-01-23
申请号：US16582919
申请日：2019-09-25
Applicant: Intel Corporation
Inventor： Michael Kounavis , David Koufaty , Anna Trikalinou , Rupin Vakharwala
IPC: G06F12/1027 , G06F12/0831 , G06F12/0868 , G06F12/14 , G11C15/04
Abstract: Embodiments are directed to providing a secure address translation service. An embodiment of a system includes a memory for storage of data, an Input/Output Memory Management Unit (IOMMU) coupled to the memory via a host-to-device link the IOMMU to perform operations, comprising receiving a memory access request from a remote device via a host-to-device link, wherein the memory access request comprises a host physical address (HPA) that identifies a physical address within the memory pertaining to the memory access request and a first message authentication code (MAC), generating a second message authentication code (MAC) using the host physical address received with the memory access request and a private key associated with the remote device, and performing at least one of allowing the memory access to proceed when the first MAC and the second MAC match and the HPA is not in an invalidation tracking table (ITT) maintained by the IOMMU; or blocking the memory operation when the first MAC and the second MAC do not match.
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