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公开(公告)号：US10296366B2
公开(公告)日：2019-05-21
申请号：US15391576
申请日：2016-12-27
Applicant: Intel Corporation
Inventor： Gilbert Neiger , Mayank Bomb , Manohar Castelino , Robert Chappell , David Durham , Barry Huntley , Anton Ivanov , Madhavan Parthasarathy , Scott Rodgers , Ravi Sahita , Vedvyas Shanbhogue
Abstract: Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to enter a virtual machine. The control logic is to determine, in response to a privileged event occurring within the virtual machine, whether to generate a virtualization exception. The execution hardware is to generate a virtualization exception in response to the control logic determining to generate a virtualization exception.
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公开(公告)号：US09769123B2
公开(公告)日：2017-09-19
申请号：US13863168
申请日：2013-04-15
Applicant: Intel Corporation
Inventor： Karanvir S. Grewal , Ravi L. Sahita , David Durham
CPC classification number: H04L63/0428 , G06F21/52 , G06F21/53 , G06F21/606 , G06F21/78 , G06F21/85
Abstract: One particular example implementation of an apparatus for mitigating unauthorized access to data traffic, comprises: an operating system stack to allocate unprotected kernel transfer buffers; a hypervisor to allocate protected memory data buffers, where data is to be stored in the protected memory data buffers before being copied to the unprotected kernel transfer buffers; and an encoder module to encrypt the data stored in the protected memory data buffers, where the unprotected kernel transfer buffers receive a copy the encrypted data.
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公开(公告)号：US09563455B2
公开(公告)日：2017-02-07
申请号：US14064759
申请日：2013-10-28
Applicant: Intel Corporation
Inventor： Gilbert Neiger , Mayank Bomb , Manohar Castelino , Robert Chappell , David Durham , Barry Huntley , Anton Ivanov , Madhavan Parthasarathy , Scott Rodgers , Ravi Sahita , Vedvyas Shanbhogue
CPC classification number: G06F9/45558 , G06F9/30076 , G06F9/45533 , G06F9/4555 , G06F9/4812 , G06F11/07 , G06F2009/45583
Abstract: Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to enter a virtual machine. The control logic is to determine, in response to a privileged event occurring within the virtual machine, whether to generate a virtualization exception. The execution hardware is to generate a virtualization exception in response to the control logic determining to generate a virtualization exception.
Abstract translation: 公开了用于虚拟化异常的发明的实施例。 在一个实施例中，处理器包括指令硬件，控制逻辑和执行硬件。 指令硬件是接收多个指令，包括进入虚拟机的指令。 控制逻辑是为了响应在虚拟机内发生的特权事件来确定是否生成虚拟化异常。 执行硬件是响应于控制逻辑确定生成虚拟化异常来生成虚拟化异常。
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公开(公告)号：US11568211B2
公开(公告)日：2023-01-31
申请号：US16233700
申请日：2018-12-27
Applicant: Intel Corporation
Inventor： David Durham , Michael Kounavis , Oleg Pogorelik , Alex Nayshtut , Omer Ben-Shalom , Antonios Papadimitriou
Abstract: The present disclosure is directed to systems and methods for the selective introduction of low-level pseudo-random noise into at least a portion of the weights used in a neural network model to increase the robustness of the neural network and provide a stochastic transformation defense against perturbation type attacks. Random number generation circuitry provides a plurality of pseudo-random values. Combiner circuitry combines the pseudo-random values with a defined number of least significant bits/digits in at least some of the weights used to provide a neural network model implemented by neural network circuitry. In some instances, selection circuitry selects pseudo-random values for combination with the network weights based on a defined pseudo-random value probability distribution.
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公开(公告)号：US11520611B2
公开(公告)日：2022-12-06
申请号：US16370924
申请日：2019-03-30
Applicant: Intel Corporation
Inventor： David Durham , Siddhartha Chhabra , Geoffrey Strongin , Ronald Perez
IPC: G06F9/455 , G06F12/1009 , H04L9/32
Abstract: A host Virtual Machine Monitor (VMM) operates “blindly,” without the host VMM having the ability to access data within a guest virtual machine (VM) or the ability to access directly control structures that control execution flow of the guest VM. Guest VMs execute within a protected region of memory (called a key domain) that even the host VMM cannot access. Virtualization data structures that pertain to the execution state (e.g., a Virtual Machine Control Structure (VMCS)) and memory mappings (e.g., Extended Page Tables (EPTs)) of the guest VM are also located in the protected memory region and are also encrypted with the key domain key. The host VMM and other guest VMs, which do not possess the key domain key for other key domains, cannot directly modify these control structures nor access the protected memory region. The host VMM, however, using VMPageIn and VMPageOut instructions, can build virtual machines in key domains and page VM pages in and out of key domains.
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Patent Agency Ranking
公开(公告)号：US11216556B2
公开(公告)日：2022-01-04
申请号：US16222785
申请日：2018-12-17
Applicant: Intel Corporation
Inventor： Ken Grewal , Ravi Sahita , David Durham , Erdem Aktas , Sergej Deutsch , Abhishek Basak
Abstract: The present disclosure is directed to systems and methods that maintain consistency between a system architectural state and a microarchitectural state in the system cache circuitry to prevent a side-channel attack from accessing secret information. Speculative execution of one or more instructions by the processor circuitry causes memory management circuitry to transition the cache circuitry from a first microarchitectural state to a second microarchitectural state. The memory management circuitry maintains the cache circuitry in the second microarchitectural state in response to a successful completion and/or retirement of the speculatively executed instruction. The memory management circuitry reverts the cache circuitry from the second microarchitectural state to the first microarchitectural state in response to an unsuccessful completion, flushing, and/or retirement of the speculatively executed instruction.
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公开(公告)号：US10901772B2
公开(公告)日：2021-01-26
申请号：US16380717
申请日：2019-04-10
Applicant: Intel Corporation
Inventor： Gilbert Neiger , Mayank Bomb , Manohar Castelino , Robert Chappell , David Durham , Barry Huntley , Anton Ivanov , Madhavan Parthasarathy , Scott Rodgers , Ravi Sahita , Vedvyas Shanbhogue
Abstract: Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to enter a virtual machine. The control logic is to determine, in response to a privileged event occurring within the virtual machine, whether to generate a virtualization exception. The execution hardware is to generate a virtualization exception in response to the control logic determining to generate a virtualization exception.
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公开(公告)号：US20200057664A1
公开(公告)日：2020-02-20
申请号：US16370924
申请日：2019-03-30
Applicant: Intel Corporation
Inventor： David Durham , Siddhartha Chhabra , Geoffrey Strongin , Ronald Perez
IPC: G06F9/455 , G06F12/1009 , H04L9/32
Abstract: A host Virtual Machine Monitor (VMM) operates “blindly,” without the host VMM having the ability to access data within a guest virtual machine (VM) or the ability to access directly control structures that control execution flow of the guest VM. Guest VMs execute within a protected region of memory (called a key domain) that even the host VMM cannot access. Virtualization data structures that pertain to the execution state (e.g., a Virtual Machine Control Structure (VMCS)) and memory mappings (e.g., Extended Page Tables (EPTs)) of the guest VM are also located in the protected memory region and are also encrypted with the key domain key. The host VMM and other guest VMs, which do not possess the key domain key for other key domains, cannot directly modify these control structures nor access the protected memory region. The host VMM, however, using VMPageIn and VMPageOut instructions, can build virtual machines in key domains and page VM pages in and out of key domains.
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公开(公告)号：US10929527B2
公开(公告)日：2021-02-23
申请号：US15848962
申请日：2017-12-20
Applicant: INTEL CORPORATION
Inventor： Michael Kounavis , David Durham , Sergej Deutsch , Saeedeh Komijani , Amitabh Das
Abstract: Logic may implement implicit integrity techniques to maintain integrity of data. Logic may perform operations on data stored in main memory, cache, flash, data storage, or any other memory. Logic may perform more than one pattern check to determine repetitions of entities within the data. Logic may determine entropy index values and/or Boolean values and/or may compare the results to threshold values to determine if a data unit is valid. Logic may merge a tag with the data unit without expanding the data unit to create an encoded data unit. Logic may decode and process the encoded data unit to determine the data unit and the tag. Logic may determine value histograms for two or more entities, determine a sum of repetitions of the two or more entities, and compare the sum to a threshold value. Logic may determine that a data unit is valid or is corrupted.
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公开(公告)号：US10885202B2
公开(公告)日：2021-01-05
申请号：US16123593
申请日：2018-09-06
Applicant: Intel Corporation
Inventor： Francis X. McKeen , Carlos V. Rozas , Uday R. Savagaonkar , Simon P. Johnson , Vincent Scarlata , Michael A. Goldsmith , Ernie Brickell , Jiang Tao Li , Howard C. Herbert , Prashant Dewan , Stephen J. Tolopka , Gilbert Neiger , David Durham , Gary Graunke , Bernard Lint , Don A. Van Dyke , Joseph Cihula , Stalinselvaraj Jeyasingh , Stephen R. Van Doren , Dion Rodgers , John Garney , Asher Altman
Abstract: A technique to enable secure application and data integrity within a computer system. In one embodiment, one or more secure enclaves are established in which an application and data may be stored and executed.
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