公开(公告)号：US09501129B2

公开(公告)日：2016-11-22

申请号：US13780052

申请日：2013-02-28

申请人： Intel Corporation

发明人： Krishnakanth Sistla ,  Dean Mulla ,  Vivek Garg ,  Mark Rowland ,  Suresh Doraiswamy ,  Ganapati Srinivasa ,  Jeffrey D. Gilbert

IPC分类号： G06F1/32 ,  G06F13/40

CPC分类号： G06F1/324 ,  G06F13/4022 ,  Y02D10/126

摘要： In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion of non-core circuitry of the processor. This non-core portion can include a cache memory, a cache controller, and an interconnect structure. In addition to this variable frequency domain, the processor can further have a fixed frequency domain including a power control unit (PCU). This unit may be configured to cause a frequency change to the variable frequency domain without draining the non-core portion of pending transactions. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括具有包括多个核心的可变频域和该处理器的至少一部分非核心电路的多核处理器。 该非核心部分可以包括高速缓冲存储器，高速缓存控制器和互连结构。 除了该可变频域之外，处理器还可以具有包括功率控制单元（PCU）的固定频域。 该单元可以被配置为引起对可变频域的频率改变，而不会排除待处理事务的非核心部分。 描述和要求保护其他实施例。

公开(公告)号：US10078592B2

公开(公告)日：2018-09-18

申请号：US15671952

申请日：2017-08-08

申请人： Intel Corporation

发明人： Krishnakanth V. Sistla ,  Yen-Cheng Liu ,  Zhong-Ning Cai ,  Jeffrey D. Gilbert

IPC分类号： G06F12/08 ,  G06F12/084 ,  G06F12/0815

CPC分类号： G06F12/084 ,  G06F12/0815

摘要： Preventing request conflicts within microprocessors and/or computer systems. More particularly, embodiments of the invention relate to a technique to manage request conflicts within a processor and/or computer system in which a number of accesses may be made to a particular cache or group of caches shared amongst a set of cores or processors or agents.