公开(公告)号：US20040118597A1

公开(公告)日：2004-06-24

申请号：US10329188

申请日：2002-12-23

Applicant: Intel Corporation

Inventor： Weston Roth ,  Jayne L. Mershon ,  Xang Moua ,  Jason A. Mix

IPC: H05K001/03

CPC classification number: H05K1/0234 ,  H05K1/0225 ,  H05K1/0227 ,  H05K1/023 ,  H05K1/167 ,  H05K2201/0195 ,  H05K2201/0323 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09663 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49163 ,  Y10T29/49165

Abstract: The invention relates to an apparatus and method for improving coupling across plane discontinuities on circuit boards. A circuit board includes a discontinuity, e.g., a split, slot, or cutout, formed on a voltage reference plane. A conductive layer overlies the discontinuity. The conductive layer has a first portion connected to the underlying reference plane and a second portion spanning the discontinuity. The first portion is connected to the reference plane using a slot or vias. And the conductive layer has a third portion extending over the reference plane but remaining disconnected from it. The conductive layer might be graphite or carbon black.

Abstract translation: 本发明涉及一种用于改善电路板上的平面不连续性的耦合的装置和方法。 电路板包括形成在电压参考平面上的不连续性，例如分裂，槽或切口。 导电层覆盖不连续点。 导电层具有连接到下面的参考平面的第一部分和跨越不连续部分的第二部分。 第一部分使用插槽或通孔连接到参考平面。 并且导电层具有在参考平面上延伸但保持与其断开的第三部分。 导电层可以是石墨或炭黑。

公开(公告)号：US20030101585A1

公开(公告)日：2003-06-05

申请号：US10348159

申请日：2003-01-21

Applicant: Intel Corporation

Inventor： Tom E. Pearson ,  Carolyn R. McCormick ,  Jayne L. Mershon

IPC: H01K003/10 ,  H05K003/34 ,  H01R009/00 ,  H05K013/00

CPC classification number: H05K1/113 ,  H05K1/0231 ,  H05K1/114 ,  H05K3/3442 ,  H05K2201/10636 ,  H05K2203/0455 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49165 ,  Y10T29/49169

Abstract: According to a method of mounting electronic components on a printed circuit board (PCB), the electrical contacts of the components are coupled to PCB bonding pads that are intersected by via pads. To minimize various defects encountered during solder reflow, while concurrently minimizing PCB area and manufacturing costs, the via pads are formed so that the via holes substantially avoid underlying the solder fillets coupling the component contacts to the PCB bonding pads. In one embodiment, the via pads are formed in the inter-pad space beneath the component; in another embodiment they are offset from the bonding pads. A substrate, an electronic assembly, and an electronic system are also described.

Abstract translation: 根据将电子部件安装在印刷电路板（PCB）上的方法，部件的电触点耦合到通过焊盘相交的PCB焊盘。 为了最小化焊料回流期间遇到的各种缺陷，同时最小化PCB面积和制造成本，通孔焊盘形成为使得通孔基本上避免了将部件触点耦合到PCB焊盘的焊料芯下面。 在一个实施例中，通孔焊盘形成在部件下方的垫间空间中; 在另一个实施例中，它们偏离接合焊盘。 还描述了基板，电子组件和电子系统。

公开(公告)号：US20020195269A1

公开(公告)日：2002-12-26

申请号：US09887597

申请日：2001-06-22

Applicant: Intel Corporation

Inventor： Tom E. Pearson ,  Carolyn R. McCormick ,  Jayne L. Mershon

IPC: H05K001/16

CPC classification number: H05K1/113 ,  H05K1/0231 ,  H05K1/114 ,  H05K3/3442 ,  H05K2201/10636 ,  H05K2203/0455 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49165 ,  Y10T29/49169

Abstract: According to a method of mounting electronic components on a printed circuit board (PCB), the electrical contacts of the components are coupled to PCB bonding pads that are intersected by via pads. To minimize various defects encountered during solder reflow, while concurrently minimizing PCB area and manufacturing costs, the via pads are formed so that the via holes substantially avoid underlying the solder fillets coupling the component contacts to the PCB bonding pads. In one embodiment, the via pads are formed in the inter-pad space beneath the component; in another embodiment they are offset from the bonding pads. A substrate, an electronic assembly, and an electronic system are also described.

Abstract translation: 根据将电子部件安装在印刷电路板（PCB）上的方法，部件的电触点耦合到通过焊盘相交的PCB焊盘。 为了最小化焊料回流期间遇到的各种缺陷，同时最小化PCB面积和制造成本，通孔焊盘形成为使得通孔基本上避免了将部件触点耦合到PCB焊盘的焊料芯下面。 在一个实施例中，通孔焊盘形成在部件下方的垫间空间中; 在另一个实施例中，它们偏离接合焊盘。 还描述了基板，电子组件和电子系统。