公开(公告)号：US20040118597A1

公开(公告)日：2004-06-24

申请号：US10329188

申请日：2002-12-23

Applicant: Intel Corporation

Inventor： Weston Roth ,  Jayne L. Mershon ,  Xang Moua ,  Jason A. Mix

IPC: H05K001/03

CPC classification number: H05K1/0234 ,  H05K1/0225 ,  H05K1/0227 ,  H05K1/023 ,  H05K1/167 ,  H05K2201/0195 ,  H05K2201/0323 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09663 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49163 ,  Y10T29/49165

Abstract: The invention relates to an apparatus and method for improving coupling across plane discontinuities on circuit boards. A circuit board includes a discontinuity, e.g., a split, slot, or cutout, formed on a voltage reference plane. A conductive layer overlies the discontinuity. The conductive layer has a first portion connected to the underlying reference plane and a second portion spanning the discontinuity. The first portion is connected to the reference plane using a slot or vias. And the conductive layer has a third portion extending over the reference plane but remaining disconnected from it. The conductive layer might be graphite or carbon black.

Abstract translation: 本发明涉及一种用于改善电路板上的平面不连续性的耦合的装置和方法。 电路板包括形成在电压参考平面上的不连续性，例如分裂，槽或切口。 导电层覆盖不连续点。 导电层具有连接到下面的参考平面的第一部分和跨越不连续部分的第二部分。 第一部分使用插槽或通孔连接到参考平面。 并且导电层具有在参考平面上延伸但保持与其断开的第三部分。 导电层可以是石墨或炭黑。

公开(公告)号：US20030063677A1

公开(公告)日：2003-04-03

申请号：US09968641

申请日：2001-09-28

Applicant: Intel Corporation

Inventor： Jason A. Mix ,  Michael W. Leddige ,  Howard L. Heck

IPC: H04L027/00

CPC classification number: H04L25/4917 ,  H04L25/497

Abstract: A method and apparatus for the multi-level coding for communication for computer bus data transfers are described. An input signal and delayed versions of the input are combined to create an encoded output signal. An input signal and delayed versions of the output are combined to create a decoded output signal.

Abstract translation: 描述了用于计算机总线数据传输的通信的多级编码的方法和装置。 输入信号和延迟版本的输入被组合以产生编码的输出信号。 输入信号和输出的延迟版本被组合以产生解码的输出信号。