公开(公告)号：US20150286568A1

公开(公告)日：2015-10-08

申请号：US14741624

申请日：2015-06-17

Applicant: Intel Corporation

Inventor： Zeev Offen ,  Alon Naveh ,  Iris Sorani

IPC: G06F12/08

CPC classification number: G06F12/0806 ,  G06F9/3009 ,  G06F12/084 ,  G06F2201/885 ,  G06F2212/1016 ,  G06F2212/284 ,  G06F2212/62

Abstract: A method and apparatus for monitor and mwait in a distributed cache architecture is disclosed. One embodiment includes an execution thread sending a MONITOR request for an address to a portion of a distributed cache that stores the data corresponding to that address. At the distributed cache portion the MONITOR request and an associated speculative state is recorded locally for the execution thread. The execution thread then issues an MWAIT instruction for the address. At the distributed cache portion the MWAIT and an associated wait-to-trigger state are recorded for the execution thread. When a write request matching the address is received at the distributed cache portion, a monitor-wake event is then sent to the execution thread and the associated monitor state at the distributed cache portion for that execution thread can be reset to idle.

公开(公告)号：US09239789B2

公开(公告)日：2016-01-19

申请号：US14741624

申请日：2015-06-17

Applicant: Intel Corporation

Inventor： Zeev Offen ,  Alon Naveh ,  Iris Sorani

IPC: G06F12/08 ,  G06F9/30

CPC classification number: G06F12/0806 ,  G06F9/3009 ,  G06F12/084 ,  G06F2201/885 ,  G06F2212/1016 ,  G06F2212/284 ,  G06F2212/62

Abstract: A method and apparatus for monitor and mwait in a distributed cache architecture is disclosed. One embodiment includes an execution thread sending a MONITOR request for an address to a portion of a distributed cache that stores the data corresponding to that address. At the distributed cache portion the MONITOR request and an associated speculative state is recorded locally for the execution thread. The execution thread then issues an MWAIT instruction for the address. At the distributed cache portion the MWAIT and an associated wait-to-trigger state are recorded for the execution thread. When a write request matching the address is received at the distributed cache portion, a monitor-wake event is then sent to the execution thread and the associated monitor state at the distributed cache portion for that execution thread can be reset to idle.

Abstract translation: 公开了一种用于在分布式高速缓存架构中进行监视和等待的方法和装置。 一个实施例包括向存储对应于该地址的数据的分布式高速缓存的一部分发送对地址的MONITOR请求的执行线程。 在分布式缓存部分，MONITOR请求和关联的推测状态被本地记录在执行线程上。 执行线程然后发出地址的MWAIT指令。 在分布式缓存部分，为执行线程记录MWAIT和关联的等待触发状态。 当在分布式高速缓存部分接收到与该地址匹配的写入请求时，监视器 - 唤醒事件然后被发送到执行线程，并且用于该执行线程的分布式高速缓存部分处的关联监视状态可以被重置为空闲。

公开(公告)号：US09720843B2

公开(公告)日：2017-08-01

申请号：US13729439

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Gur Hildesheim ,  Shlomo Raikin ,  Ittai Anati ,  Gideon Gerzon ,  Hisham Shafi ,  Alex Berenzon ,  Geoffrey S. Strongin ,  Iris Sorani

IPC: G06F12/00 ,  G06F12/1027 ,  G06F12/14

CPC classification number: G06F12/1027 ,  G06F12/1441 ,  G06F12/145 ,  G06F2212/1052

Abstract: A processor of an aspect includes operation mode check logic to determine whether to allow an attempted access to an operation mode and access type protected memory based on an operation mode that is to indicate whether the attempted access is by an on-die processor logic. Access type check logic is to determine whether to allow the attempted access to the operation mode and access type protected memory based on an access type of the attempted access to the operation mode and access type protected memory. Protection logic is coupled with the operation mode check logic and is coupled with the access type check logic. The protection logic is to deny the attempted access to the operation mode and access type protected memory if at least one of the operation mode check logic and the access type check logic determines not to allow the attempted access.