公开(公告)号：US20230315596A1

公开(公告)日：2023-10-05

申请号：US18332420

申请日：2023-06-09

Applicant: Intel Corporation

Inventor： Aruni P. Nelson ,  Enrico David Carrieri ,  Rolf Kuehnis

IPC: G06F11/22

CPC classification number: G06F11/2273

Abstract: Embodiments herein relate to a logic configured to: identify, based on a header of a first packet, that the first packet is related to a first debug process of a component to which the logic is communicatively coupled, wherein the first debug process is performed by a first DTS; identify, based on a header of a second packet, that the second packet is related to a second debug process of the component, wherein the second debug process is performed by a second DTS; route, based on the identification that the first packet is related to the first debug process, the first packet between the component and the DTS; and route, based on the identification that the second packet is related to the second debug process, the second packet between the component and the DTS. Other embodiments may be described and/or claimed.

公开(公告)号：US20240111701A1

公开(公告)日：2024-04-04

申请号：US18539063

申请日：2023-12-13

Applicant: Intel Corporation

Inventor： Aruni P. Nelson ,  Enrico David Carrieri ,  Rolf Kuehnis ,  Peter Onufryk ,  Sridhar Muthrasanallur

IPC: G06F13/40 ,  G06F13/22 ,  G06F13/42

CPC classification number: G06F13/4031 ,  G06F13/225 ,  G06F13/4221

Abstract: Embodiments herein relate to a universal component interconnect express (UCIe) link that includes a mainband and a sideband. One or more pieces of logic may identify a data that is to be transmitted on the sideband. The logic may then identify, based on factors such as a characteristic of the data or a characteristic of the link, whether to transmit the data on the mainband. Other embodiments may be described and/or claimed.

公开(公告)号：US20220006883A1

公开(公告)日：2022-01-06

申请号：US17476618

申请日：2021-09-16

Applicant: Intel Corporation

Inventor： Amit Srivastava ,  Matthew A. Schnoor ,  Rajesh Bhaskar ,  Aruni P. Nelson ,  Enrico David Carrieri ,  Devon Worrell

IPC: H04L29/06 ,  H04L12/40

Abstract: In one embodiment, an apparatus includes a unified adapter layer and a first bus controller. The unified adapter layer is to receive a first host data packet packetized in accordance with a host protocol and directed to a first device and decode the first host data packet to generate first and second data elements based on the first host data packet, the first device associated with a first device protocol. The first bus controller is coupled to the unified adapter layer and is to be coupled to the first device via a first bus. The first bus controller is to packetize the first data element in accordance with the first device protocol to generate a first device data packet for transmission to the first device in accordance with the first device protocol via the first bus and adjust a bus controller parameter based in part on the second data element. Other embodiments are described and claimed.

公开(公告)号：US20240281403A1

公开(公告)日：2024-08-22

申请号：US18648648

申请日：2024-04-29

Applicant: Intel Corporation

Inventor： Janusz Jurski ,  Enrico David Carrieri ,  Amit Kumar Srivastava ,  Matthew A. Schnoor ,  Myron Loewen

IPC: G06F13/42 ,  G06F9/54 ,  G06F13/24 ,  G06F13/362

CPC classification number: G06F13/4291 ,  G06F9/542 ,  G06F13/24 ,  G06F13/362

Abstract: Embodiments of the present disclosure may relate to apparatus, process, or techniques in a I3C protocol environment that include identifying a pending read notification message by a slave device to be sent to a master device to indicate that the data is available to be read by the master device from a buffer associated with the slave device. The pending read notification may be subsequently transmitted to the master device. Subsequently, until the data in the buffer has been read by the master device, the slave device may wait an identified amount of time that is less than a value of a timeout of the master device, and retransmit the pending read notification message to the master device. Other embodiments may be described and/or claimed.

公开(公告)号：US12013806B2

公开(公告)日：2024-06-18

申请号：US17128384

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Janusz Jurski ,  Enrico David Carrieri ,  Amit Kumar Srivastava ,  Matthew A. Schnoor ,  Myron Loewen

IPC: G06F13/42 ,  G06F9/54 ,  G06F13/24 ,  G06F13/362

CPC classification number: G06F13/4291 ,  G06F9/542 ,  G06F13/24 ,  G06F13/362

Abstract: Embodiments of the present disclosure may relate to apparatus, process, or techniques in a I3C protocol environment that include identifying a pending read notification message by a slave device to be sent to a master device to indicate that the data is available to be read by the master device from a buffer associated with the slave device. The pending read notification may be subsequently transmitted to the master device. Subsequently, until the data in the buffer has been read by the master device, the slave device may wait an identified amount of time that is less than a value of a timeout of the master device, and retransmit the pending read notification message to the master device. Other embodiments may be described and/or claimed.

公开(公告)号：US11734457B2

公开(公告)日：2023-08-22

申请号：US16724555

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Neel Piyush Shah ,  Enrico David Carrieri ,  Aditya Katragada ,  Jonathan Mark Lutz ,  Michael Carl Neve de Mevergnies ,  Bhavana Prabhakar

IPC: G06F21/71 ,  G06F11/36 ,  G06F21/31 ,  G06F21/79

CPC classification number: G06F21/71 ,  G06F11/3656 ,  G06F21/31 ,  G06F21/79

Abstract: A processor that was manufactured by a manufacturer comprises privileged debug operational circuitry, a debug restriction fuse, a credential store, a credential of the manufacturer in the credential store, and debug control circuitry. The debug restriction fuse is a one-time programmable fuse. The debug control circuitry is to automatically restrict access to the privileged debug operational circuitry, based on the debug restriction fuse. The processor may also include public debug operational circuitry, a prevent-unauthorized-debug (PUD) fuse, and an undo-PUD fuse. When the PUD fuse is set and the undo-PUD fuse is clear, the debug control circuitry may respond to an attempt by a debugger to use the public debug operational circuitry by determining whether the debugger is authorized, disallowing access if the debugger is not authorized, and allowing access if the debugger is authorized. Other embodiments are described and claimed.