公开(公告)号：US10649772B2

公开(公告)日：2020-05-12

申请号：US15941526

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Dennis Ryan Bradford ,  Jesus Corbal ,  Brian Hickmann ,  Rohan Sharma

IPC: G06F9/315 ,  G06F17/16 ,  G06F7/78 ,  G06F9/30 ,  G06F9/38

Abstract: Disclosed embodiments relate to a method and apparatus for efficient matrix transpose. In one example, a processor to execute a matrix transpose instruction includes fetch circuitry to fetch the matrix transpose instruction specifying a destination matrix and a source matrix having (N×M) elements and (M×N) elements, respectively, a (N×M) load buffer, decode circuitry to decode the fetched matrix transpose instruction, and execution circuitry, responsive to the decoded matrix transpose instruction to, for each row X of M rows of the specified source matrix: fetch and buffer N elements of the row in a load register, and cause the N buffered elements to be written, in the same relative order as in the row, to column X of M columns of the load buffer, and the execution circuitry subsequently to write each of N rows of the load buffer to a same row of the load buffer.

公开(公告)号：US09654143B2

公开(公告)日：2017-05-16

申请号：US14308107

申请日：2014-06-18

Applicant: Intel Corporation

Inventor： Guillem Sole ,  Roger Espasa ,  Sorin Iacobovici ,  Brian Hickmann ,  Wei Wu ,  Thomas Fletcher

IPC: G06F11/10 ,  H03M13/09 ,  H03M13/17 ,  H03M13/19 ,  H03M13/29

CPC classification number: H03M13/09 ,  G06F11/1012 ,  H03M13/17 ,  H03M13/19 ,  H03M13/29

Abstract: Embodiments of an invention for consecutive bit error detection and correction are disclosed. In one embodiment, an apparatus includes a storage structure, a second storage structure, a parity checker, an error correction code (ECC) checker, and an error corrector. The first storage structure is to store a plurality of data values, a plurality of parity values, and a plurality of ECC values, each parity value corresponding to one of the plurality of data values, a first bit of each parity value corresponding to a first of a plurality of portions of a corresponding data value, wherein the first of the plurality of portions of the corresponding data value is interleaved with a second of the plurality of portions of the corresponding data value, wherein a second bit of each parity value corresponds to a second of the plurality of portions of the corresponding data value, each ECC value corresponding to one of the plurality of data values. The parity checker is to detect a parity error in a data value stored in the first storage structure using a parity value corresponding to the data value. The ECC checker is to generate a syndrome. The error corrector is to detect and correct consecutive bit errors in the data value using the syndrome.