公开(公告)号：US10925152B2

公开(公告)日：2021-02-16

申请号：US16146168

申请日：2018-09-28

申请人： Intel Corporation

发明人： Albert Sutono ,  Xiaoning Ye ,  Jimmy Hsu ,  Daniel Hull

IPC分类号： H05K1/02 ,  H05K3/34 ,  H01L23/00 ,  H01L23/538 ,  H01L23/498 ,  H05K3/28

摘要： Apparatuses, systems and methods associated with dielectric coatings for printed circuit boards are disclosed herein. In embodiments, a printed circuit board (PCB) includes a substrate, microstrip conductors located on a surface of the substrate, a solder mask covering the surface of the substrate and the microstrip conductors, and a dielectric coating located on the solder mask, the dielectric coating on an opposite side of the solder mask from the microstrip conductors, wherein a thickness of the dielectric coating is selected to cause a ratio of capacitive coupling to self capacitance to be approximately equal to a ratio of inductive coupling to self inductance for each microstrip conductor of the microstrip conductors, where the thickness may be determined based on a specific methodology including simulations. Other embodiments may be described and/or claimed.

公开(公告)号：US20190045623A1

公开(公告)日：2019-02-07

申请号：US16146168

申请日：2018-09-28

申请人： Intel Corporation

发明人： Albert Sutono ,  Xiaoning Ye ,  Jimmy Hsu ,  Daniel Hull

IPC分类号： H05K1/02 ,  H05K3/34 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

摘要： Apparatuses, systems and methods associated with dielectric coatings for printed circuit boards are disclosed herein. In embodiments, a printed circuit board (PCB) includes a substrate, microstrip conductors located on a surface of the substrate, a solder mask covering the surface of the substrate and the microstrip conductors, and a dielectric coating located on the solder mask, the dielectric coating on an opposite side of the solder mask from the microstrip conductors, wherein a thickness of the dielectric coating is selected to cause a ratio of capacitive coupling to self capacitance to be approximately equal to a ratio of inductive coupling to self inductance for each microstrip conductor of the microstrip conductors, where the thickness may be determined based on a specific methodology including simulations. Other embodiments may be described and/or claimed.

公开(公告)号：US12113265B2

公开(公告)日：2024-10-08

申请号：US17214111

申请日：2021-03-26

申请人： Intel Corporation

发明人： Albert Sutono ,  Xiaoning Ye

IPC分类号： H01L23/49 ,  H01L23/498 ,  H01L23/528 ,  H01L23/66 ,  H01P3/08 ,  H05K1/02

CPC分类号： H01P3/08 ,  H01L23/49838 ,  H01L23/5283 ,  H01L23/66 ,  H05K1/0228 ,  H01L23/49822 ,  H01L2223/6627

摘要： Electronic structures including a dual-stripline with crosstalk cancellation are described. In an example, a printed circuit board (PCB), a package substrate or a semiconductor die includes a dual-stripline structure. The dual-stripline structure includes a first region including a first top line vertically over a first bottom line, and a second top line vertically over a second bottom line. The dual-stripline structure also includes a second region including the first top line vertically over the second bottom line, and the second top line vertically over the first bottom line. The dual-stripline structure also includes a transition region between the first region and the second region. The first bottom line and the second bottom line cross in the transition region.

公开(公告)号：US20220270989A1

公开(公告)日：2022-08-25

申请号：US17183572

申请日：2021-02-24

申请人： Intel Corporation

发明人： Albert Sutono ,  Xiaoning Ye

IPC分类号： H01L23/66

摘要： Disclosed herein are integrated circuit (IC) supports with microstrips, and related embodiments. For example, an IC support may include a first microstrip; a first surface dielectric region over the first microstrip, wherein the first surface dielectric region has a first thickness, and the first thickness is nonzero; a second microstrip; and a second surface dielectric region over the second microstrip, wherein the second surface dielectric region has a second thickness, the second thickness is nonzero, and the first thickness is different than the second thickness.

公开(公告)号：US10607952B2

公开(公告)日：2020-03-31

申请号：US16116483

申请日：2018-08-29

申请人： Intel Corporation

发明人： Albert Sutono

IPC分类号： H01L23/528 ,  H01L23/66 ,  H01L23/538 ,  H01L25/065 ,  H01P3/08 ,  H01L23/00

摘要： In accordance with embodiments disclosed herein, there is provided a high density triple diamond stripline interconnect. An interconnect includes a first reference layer, a second reference layer disposed below the first reference layer, and a dielectric disposed between the first reference layer and the second reference layer. The interconnect further includes a first pair of conductors including a first conductor and a second conductor that are in a broadside-facing orientation within the dielectric below the first reference layer and above the second reference layer. The interconnect further includes a second pair of conductors including a third conductor and a fourth conductor that are in an edge-facing orientation within the dielectric below the first conductor and above the second conductor.

公开(公告)号：US20190043816A1

公开(公告)日：2019-02-07

申请号：US16116483

申请日：2018-08-29

申请人： Intel Corporation

发明人： Albert Sutono

IPC分类号： H01L23/66 ,  H01L23/538 ,  H01L25/065 ,  H01L23/528 ,  H01P3/08

摘要： In accordance with embodiments disclosed herein, there is provided a high density triple diamond stripline interconnect. An interconnect includes a first reference layer, a second reference layer disposed below the first reference layer, and a dielectric disposed between the first reference layer and the second reference layer. The interconnect further includes a first pair of conductors including a first conductor and a second conductor that are in a broadside-facing orientation within the dielectric below the first reference layer and above the second reference layer. The interconnect further includes a second pair of conductors including a third conductor and a fourth conductor that are in an edge-facing orientation within the dielectric below the first conductor and above the second conductor.