公开(公告)号：US10811558B2

公开(公告)日：2020-10-20

申请号：US16317135

申请日：2017-06-22

Applicant: Institutt for Energiteknikk ,  Universidad Complutense de Madrid

Inventor： Ana Cremades Rodriguez ,  Chang Chuan You ,  David Maestre Varea ,  Erik Stensrud Marstein ,  Geraldo Cristian Vasquez Villanueva ,  Halvard Haug ,  Javier Piqueres De Noriega ,  Jose Maria Gonzalez Calbet ,  Julio Ramirez Castellanos ,  Maria Taeno Gonzalez ,  Miguel Garcia Tecedor ,  Smagul Karazhanov

IPC: H01L31/18 ,  H01L31/04 ,  C09D5/34 ,  C09D165/00 ,  C09D7/61 ,  C09D7/40 ,  C09D7/45 ,  C09D5/24

Abstract: A relevant technological challenge is the low cost and abundant materials development for silicon surface passivation for applications in optoelectronic devices, in particular in solar cells by scalable industrial methods. In the present invention, a new hybrid material comprising PEDOT:PSS and transparent conducting oxide nanostructures is developed and a method is proposed to fabricate the composite material that passivates well the silicon surface to be used by means of a thin composite film of thickness below 200 nm.

公开(公告)号：US09660130B2

公开(公告)日：2017-05-23

申请号：US15037163

申请日：2014-11-19

Applicant: Institutt for Energiteknikk

Inventor： Junjie Zhu ,  Su Zhou ,  Halvard Haug ,  Erik Stensrud Marstein ,  Sean Erik Foss ,  Wenjing Wang ,  Chunlan Zhou

IPC: H01L31/0216 ,  H01L31/18 ,  H01L21/02 ,  H01L31/068

CPC classification number: H01L31/1804 ,  H01L21/02057 ,  H01L21/0214 ,  H01L21/02301 ,  H01L31/02167 ,  H01L31/068 ,  Y02E10/547

Abstract: A method for manufacturing a passivation stack on a crystalline silicon solar cell device. The method includes providing a substrate comprising a crystalline silicone layer such as a crystalline silicon wafer or chip, cleaning a surface of the crystalline silicon layer by removing an oxide layer at least from a portion of one side of the crystalline silicon layer, depositing, on at least a part of the cleaned surface, a layer of silicon oxynitride, and depositing a capping layer comprising a hydrogenated dielectric material on top of the layer of silicon oxynitride, wherein the layer of silicon oxynitride is deposited at a temperature from 100° C. to 200° C., and the step of depositing the layer of silicon oxynitride includes using N2O and SiH4 as precursor gasses in an N2 ambient atmosphere and depositing silicon oxynitride with a gas flow ratio of N2O to SiH4 below 2.

公开(公告)号：US09978902B2

公开(公告)日：2018-05-22

申请号：US15494064

申请日：2017-04-21

Applicant: Institutt for Energiteknikk

Inventor： Junjie Zhu ,  Su Zhou ,  Halvard Haug ,  Erik Stensrud Marstein ,  Sean Erik Foss ,  Wenjing Wang ,  Chunlan Zhou

IPC: H01L31/0216 ,  H01L31/18 ,  H01L21/02

CPC classification number: H01L31/1804 ,  H01L21/02057 ,  H01L21/0214 ,  H01L21/02301 ,  H01L31/02167 ,  H01L31/068 ,  Y02E10/547

Abstract: A method for manufacturing a passivation stack on a crystalline silicon solar cell device. The method includes providing a substrate comprising a crystalline silicone layer such as a crystalline silicon wafer or chip, cleaning a surface of the crystalline silicon layer by removing an oxide layer at least from a portion of one side of the crystalline silicon layer, depositing, on at least a part of the cleaned surface, a layer of silicon oxynitride, and depositing a capping layer comprising a hydrogenated dielectric material on top of the layer of silicon oxynitride, wherein the layer of silicon oxynitride is deposited at a temperature from 100° C. to 200° C., and the step of depositing the layer of silicon oxynitride includes using N2O and SiH4 as precursor gasses in an N2 ambient atmosphere and depositing silicon oxynitride with a gas flow ratio of N2O to SiH4 below 2.