公开(公告)号：US20230195564A1

公开(公告)日：2023-06-22

申请号：US17698729

申请日：2022-03-18

Applicant: Infineon Technologies LLC

Inventor： Yuichi Ise ,  Clifford Zitlaw ,  Nobuaki Hata

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1048 ,  G06F11/1068 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0679

Abstract: In an embodiment, a method includes: receiving, via control lines of a parallel interface of a memory device, a first command and a first read command including one or more bits indicative of a first selection that causes a selector circuit to select data from a data memory portion of the memory device; providing, via data lines of the parallel interface, first data from the data memory portion using the selector circuit, where the provided first data is associated with the first read command; receiving, via the control lines, a second command and a second read command including one or more bits indicative of a second selection that causes the selector circuit to select data from an ECC memory portion; and providing, via the data lines, first ECC values from the ECC memory portion using the selector circuit, where the first ECC values are associated with the first data.

公开(公告)号：US11562781B1

公开(公告)日：2023-01-24

申请号：US17499938

申请日：2021-10-13

Applicant: Infineon Technologies LLC

Inventor： Clifford Zitlaw ,  Stephan Rosner ,  Avi Avanindra

IPC: G11C8/00 ,  G11C7/22 ,  G11C7/10 ,  G11C8/18

Abstract: A method can include, in an integrated circuit device: at a unidirectional command-address (CA) bus having no more than four parallel inputs, receiving a sequence of no less than three command value portions; latching each command value portion in synchronism with rising edges of a timing clock; determining an input command from the sequence of no less than three command value portions; executing the input command in the integrated circuit device; and on a bi-directional data bus having no more than six data input/outputs (IOs), outputting and inputting sequences of data values in synchronism with rising and falling edges of the timing clock. Corresponding devices and systems are also disclosed.

公开(公告)号：US20230342034A1

公开(公告)日：2023-10-26

申请号：US17728783

申请日：2022-04-25

Applicant: Infineon Technologies LLC

Inventor： Nobuaki Hata ,  Clifford Zitlaw ,  Yuichi Ise ,  Stephan Rosner

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0284

Abstract: A method can include, in a default mode of a memory device, decoding command data received on a unidirectional command address (CA) bus of a memory interface according to a first standard. In response to decoding a mode enter command, placing the memory device into an alternate management mode. In the alternate management mode, receiving alternate command data on the CA bus, and in response to receiving a command execute indication on the CA bus, decoding alternate command data according to a second standard to execute an alternate command. In response to decoding a mode exit command received on the CA bus according to the first standard, returning the memory device to the default mode. The memory interface comprises the CA bus and a data bus, and the CA bus and data bus comprise a plurality of parallel input connections. Corresponding devices and systems are also disclosed.

公开(公告)号：US20220107908A1

公开(公告)日：2022-04-07

申请号：US17125927

申请日：2020-12-17

Applicant: Infineon Technologies LLC

Inventor： Clifford Zitlaw ,  Stephan Rosner ,  Hans Van Antwerpen ,  Morgan Andrew Whately

IPC: G06F13/16 ,  G06F13/28 ,  G06F13/42 ,  G06F13/40

Abstract: A method can include: receiving a plurality of consecutive commands on a unidirectional command-address (CA) bus input of a discrete nonvolatile memory (NVM) device, the commands being synchronous with a timing clock; for each received command, determining if the command is an express read (NVR) command, if a command is determined to be an NVR command, determining if a next consecutive command is an NVR command, wherein consecutive NVR commands form an NVR command sequence; in response to the no more than the NVR command sequence, accessing read data stored in NVM cells of the NVM device; and driving the read data on parallel data input/outputs (I/Os) of the NVM device in a burst of data values, the data values of the burst being output in synchronism with rising and falling edges of the timing clock; wherein the CA bus input includes a plurality of parallel CA signal inputs. Related memory devices and systems are also disclosed.

公开(公告)号：US11983411B2

公开(公告)日：2024-05-14

申请号：US17728783

申请日：2022-04-25

Applicant: Infineon Technologies LLC

Inventor： Nobuaki Hata ,  Clifford Zitlaw ,  Yuichi Ise ,  Stephan Rosner

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0611 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0284 ,  G06F2212/1024

Abstract: A method can include, in a default mode of a memory device, decoding command data received on a unidirectional command address (CA) bus of a memory interface according to a first standard. In response to decoding a mode enter command, placing the memory device into an alternate management mode. In the alternate management mode, receiving alternate command data on the CA bus, and in response to receiving a command execute indication on the CA bus, decoding alternate command data according to a second standard to execute an alternate command. In response to decoding a mode exit command received on the CA bus according to the first standard, returning the memory device to the default mode. The memory interface comprises the CA bus and a data bus, and the CA bus and data bus comprise a plurality of parallel input connections. Corresponding devices and systems are also disclosed.

公开(公告)号：US11971832B2

公开(公告)日：2024-04-30

申请号：US17125927

申请日：2020-12-17

Applicant: Infineon Technologies LLC

Inventor： Clifford Zitlaw ,  Stephan Rosner ,  Hans Van Antwerpen ,  Morgan Andrew Whately

IPC: G06F13/16 ,  G06F13/28 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/1689 ,  G06F13/28 ,  G06F13/409 ,  G06F13/4291

Abstract: A method can include: receiving a plurality of consecutive commands on a unidirectional command-address (CA) bus input of a discrete nonvolatile memory (NVM) device, the commands being synchronous with a timing clock; for each received command, determining if the command is an express read (NVR) command, if a command is determined to be an NVR command, determining if a next consecutive command is an NVR command, wherein consecutive NVR commands form an NVR command sequence; in response to the no more than the NVR command sequence, accessing read data stored in NVM cells of the NVM device; and driving the read data on parallel data input/outputs (I/Os) of the NVM device in a burst of data values, the data values of the burst being output in synchronism with rising and falling edges of the timing clock; wherein the CA bus input includes a plurality of parallel CA signal inputs. Related memory devices and systems are also disclosed.

公开(公告)号：US20210279200A1

公开(公告)日：2021-09-09

申请号：US17030664

申请日：2020-09-24

Applicant: Infineon Technologies LLC

Inventor： Clifford Zitlaw ,  Stephan Rosner

IPC: G06F13/42

Abstract: A method can include, by operation of a host device, initiating a first transaction with at least a first device on a serial bus in synchronism with a clock, the first transaction having a predetermined response latency. The host device can initiate a second transaction on the serial bus in synchronism with the clock signal during the response latency. The first transaction and second transaction can be completed on the serial bus in synchronism with the clock. The serial bus is configured to transmit instruction data identifying transactions, target data identifying a destination for transactions, and data for transactions. Corresponding devices and systems are also disclosed.

公开(公告)号：US20240345972A1

公开(公告)日：2024-10-17

申请号：US18647048

申请日：2024-04-26

Applicant: Infineon Technologies LLC

Inventor： Clifford Zitlaw ,  Stephan Rosner ,  Hans Van Antwerpen ,  Morgan Andrew Whately

IPC: G06F13/16 ,  G06F13/28 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/1689 ,  G06F13/28 ,  G06F13/409 ,  G06F13/4291

Abstract: A method can include: receiving a plurality of consecutive commands on a unidirectional command-address (CA) bus input of a discrete nonvolatile memory (NVM) device, the commands being synchronous with a timing clock; for each received command, determining if the command is an express read (NVR) command, if a command is determined to be an NVR command, determining if a next consecutive command is an NVR command, wherein consecutive NVR commands form an NVR command sequence; in response to the no more than the NVR command sequence, accessing read data stored in NVM cells of the NVM device; and driving the read data on parallel data input/outputs (I/Os) of the NVM device in a burst of data values, the data values of the burst being output in synchronism with rising and falling edges of the timing clock; wherein the CA bus input includes a plurality of parallel CA signal inputs. Related memory devices and systems are also disclosed.

公开(公告)号：US11841764B2

公开(公告)日：2023-12-12

申请号：US17698729

申请日：2022-03-18

Applicant: Infineon Technologies LLC

Inventor： Yuichi Ise ,  Clifford Zitlaw ,  Nobuaki Hata

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1048 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0679 ,  G06F11/1068

Abstract: In an embodiment, a method includes: receiving, via control lines of a parallel interface of a memory device, a first command and a first read command including one or more bits indicative of a first selection that causes a selector circuit to select data from a data memory portion of the memory device; providing, via data lines of the parallel interface, first data from the data memory portion using the selector circuit, where the provided first data is associated with the first read command; receiving, via the control lines, a second command and a second read command including one or more bits indicative of a second selection that causes the selector circuit to select data from an ECC memory portion; and providing, via the data lines, first ECC values from the ECC memory portion using the selector circuit, where the first ECC values are associated with the first data.

公开(公告)号：US11422968B2

公开(公告)日：2022-08-23

申请号：US17030664

申请日：2020-09-24

Applicant: Infineon Technologies LLC

Inventor： Clifford Zitlaw ,  Stephan Rosner

IPC: G06F13/42 ,  G06F9/38

Abstract: A method can include, by operation of a host device, initiating a first transaction with at least a first device on a serial bus in synchronism with a clock, the first transaction having a predetermined response latency. The host device can initiate a second transaction on the serial bus in synchronism with the clock signal during the response latency. The first transaction and second transaction can be completed on the serial bus in synchronism with the clock. The serial bus is configured to transmit instruction data identifying transactions, target data identifying a destination for transactions, and data for transactions. Corresponding devices and systems are also disclosed.