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    MULTIPLE SENSOR-FUSING BASED INTERACTIVE TRAINING SYSTEM AND MULTIPLE SENSOR-FUSING BASED INTERACTIVE TRAINING METHOD
    1.
    发明申请
    MULTIPLE SENSOR-FUSING BASED INTERACTIVE TRAINING SYSTEM AND MULTIPLE SENSOR-FUSING BASED INTERACTIVE TRAINING METHOD 有权

    公开(公告)号：US20230140585A1

    公开(公告)日：2023-05-04

    申请号：US17975628

    申请日：2022-10-28

    申请人： Industrial Technology Research Institute

    发明人： Hung-Hsien Ko ,  Heng-Yin Chen ,  Chen-Tsai Yang

    IPC分类号： A61B5/11 ,  A61B5/00 ,  G06K9/62

    摘要： A multiple sensor-fusing based interactive training system, including a posture sensor, a sensing module, a computing module, and a display module, is provided. The posture sensor is configured to sense posture data and myoelectric data related to a training action. The sensing module is configured to output limb torque data according to the posture data, and output muscle group activation time data according to the myoelectric data. The computing module is configured to respectively convert the limb torque data and the muscle group activation time data into a moment-skeleton coordinate system and a muscle strength eigenvalue-skeleton coordinate system according to a skeleton coordinate system, perform fusion calculation, calculate evaluation data based on a result of the fusion calculation, and judge that the training action corresponds to a known exercise action according to the evaluation data. The display module is configured to display the evaluation data and the known exercise action.

    SEMICONDUCTOR PACKAGE STRUCTURE
    2.
    发明申请
    SEMICONDUCTOR PACKAGE STRUCTURE 审中-公开

    公开(公告)号：US20190088600A1

    公开(公告)日：2019-03-21

    申请号：US15849593

    申请日：2017-12-20

    申请人： Industrial Technology Research Institute ,  Intellectual Property Innovation Corporation

    发明人： Shu-Wei Kuo ,  Wei-Yuan Cheng ,  Chen-Tsai Yang ,  Jie-Mo Lin

    IPC分类号： H01L23/538 ,  H01L23/14 ,  H01L23/15 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

    摘要： A semiconductor package structure includes a redistribution structure, a chip, an upper dielectric layer, a plurality of conductive members and an encapsulation layer. The redistribution structure includes a redistribution layer and a first dielectric layer disposed on the redistribution layer. The upper dielectric layer is disposed between the chip and the first dielectric layer of the redistribution structure, wherein the upper dielectric layer and the first dielectric layer are organic materials. A plurality of conductive members is disposed between the redistribution layer and the chip. Each conductive member has a first end adjacent to the chip and a second end adjacent to the redistribution structure, wherein the first end of said each conductive member contacts with the upper dielectric layer and the second end of said each conductive member contacts with the first dielectric layer.

    CHIP PACKAGE STRUCTURE
    3.
    发明申请
    CHIP PACKAGE STRUCTURE 审中-公开

    公开(公告)号：US20190057948A1

    公开(公告)日：2019-02-21

    申请号：US15911183

    申请日：2018-03-05

    申请人： Industrial Technology Research Institute ,  Intellectual Property Innovation Corporation

    发明人： Chen-Tsai Yang ,  Ko-Chin Yang ,  Jui-Chang Chuang ,  Yen-Ting Wu ,  Chia-Hua Lu

    IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065

    摘要： A chip package structure includes a chip package layer and at least one conductive structure layer. The chip package layer includes at least one chip and an encapsulant. The chip has an upper surface, and the encapsulant is used to encapsulate the chip and expose the upper surface. The conductive structure layer includes a plurality of first conductive pillars and a plurality of second conductive pillars. The first conductive pillars are disposed on the upper surface, the second conductive pillars are disposed on the upper surface and located between an edge of the upper surface and the first conductive pillars. A density of the second conductive pillars along an extending direction of the edge is greater than or equal to 1.2 times of a density of the first conductive pillars along the extending direction of the edge.

    ELECTRONIC DEVICE PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    6.
    发明申请
    ELECTRONIC DEVICE PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20200211984A1

    公开(公告)日：2020-07-02

    申请号：US16404765

    申请日：2019-05-07

    申请人： Industrial Technology Research Institute

    发明人： Jui-Chang Chuang ,  Chen-Tsai Yang ,  Wei-Yuan Cheng

    IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

    摘要： An electronic device package structure and a manufacturing method thereof are provided. The electronic device package structure includes a first electronic device layer, a second electronic device layer, and a filling layer disposed between the first electronic device layer and the second electronic device layer, wherein the Young's modulus of the second electronic device layer is less than or equal to the Young's modulus of the first electronic device layer, and the Young's modulus of the filling layer is less than the Young's modulus of the second electronic device layer, and the ratio of the Young's modulus of the first electronic device layer to the Young's modulus of the filling layer is 10 to 1900 and the ratio of the Young's modulus of the second electronic device layer to the Young's modulus of the filling layer is 7.6 to 1300.

    Chip package structure
    9.
    发明授权
    Chip package structure 有权

    公开(公告)号：US11362045B2

    公开(公告)日：2022-06-14

    申请号：US16792905

    申请日：2020-02-18

    申请人： Industrial Technology Research Institute

    发明人： Te-Hsun Lin ,  Chen-Tsai Yang ,  Kuan-Chu Wu ,  Shao-An Yan

    IPC分类号： H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/14 ,  H01L23/498

    摘要： A chip package structure including a substrate, a redistribution layer (RDL), a chip and an encapsulant is provided. The RDL is disposed on the substrate. The chip is disposed on the RDL and is electrically connected with the RDL. The encapsulant is disposed on the RDL and encapsulates the chip. The chip is located in the high stress region. From a top view, the chip is located in the high stress region, and the low stress region surrounds the high stress region. The RDL includes at least one first device located in the high stress region. From the top view, the extending direction of the at least one first device is parallel to a stress direction at a position thereof.

    Flexible hybrid electronic system and method of reducing the impact thereof
    10.
    发明授权
    Flexible hybrid electronic system and method of reducing the impact thereof 有权

    公开(公告)号：US10757804B1

    公开(公告)日：2020-08-25

    申请号：US16815031

    申请日：2020-03-11

    申请人： Industrial Technology Research Institute

    发明人： Yu-Ming Peng ,  Kuan-Chu Wu ,  Kai-Ming Chang ,  Chen-Tsai Yang

    IPC分类号： H05K1/11 ,  H05K1/02 ,  H01L23/498

    摘要： A flexible hybrid electronic (FHE) system includes a carrier, a first redistribution structure on the carrier, a first device on the first redistribution structure, and an encapsulation layer encapsulating the first device. The carrier has a first Young's modulus Y1. The first redistribution structure has a second Young's modulus Y2. The first device and a portion of the encapsulation layer form a top surface of the first redistribution structure to a top surface of the first device is a first portion having a third Young's modulus Y3. The other portion of the encapsulation layer from the top surface of the first device to a top surface of the encapsulation layer is a second portion having a fourth Young's modulus Y4. A ratio of Y3/Y4 is between 1.62 and 1.98; a ratio of Y3/Y2 is between 0.18 and 0.22; and a ratio of Y3/Y1 is between 280.62 and 342.98.