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公开(公告)号：US20240296085A1
公开(公告)日：2024-09-05
申请号：US18348416
申请日：2023-07-07
发明人： Nikolaos Papandreou , Timothy J. Fisher , Roman Alexander Pletka , Charalampos Pozidis , Radu Ioan Stoica , Aaron Daniel Fry , Andrew D. Walls
IPC分类号： G06F11/07
CPC分类号： G06F11/076 , G06F11/073
摘要： A technique for writing data to pages in a QLC block of a QLC NAND flash memory device, where the device comprises a plurality of SLC pages organized in SLC blocks and a plurality of QLC pages organized in QLC blocks. The technique comprises storing received data in SLC pages, dividing equally a QLC block in a predefined number of sub-blocks according to a corresponding QLC page health status of the pages of the QLC block. Upon determining that SLC pages are to be copied from SLC pages to QLC pages, copying device-internal the respective SLC pages to the sub-blocks of the QLC block using device-internal cache registers, where the copying is based on an error-count aware scheme.
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公开(公告)号：US11803779B2
公开(公告)日：2023-10-31
申请号：US16800040
申请日：2020-02-25
发明人： Thomas Parnell , Andreea Anghel , Nikolas Ioannou , Nikolaos Papandreou , Celestine Mendler-Duenner , Dimitrios Sarigiannis , Charalampos Pozidis
摘要： In an approach for constructing an ensemble model from a set of base learners, a processor performs a plurality of boosting iterations, where: at each boosting iteration of the plurality of boosting iterations, a base learner is selected at random from a set of base learners, according to a sampling probability distribution of the set of base learners, and trained according to a training dataset; and the sampling probability distribution is altered: (i) after selecting a first base learner at a first boosting iteration of the plurality of boosting iterations and (ii) prior to selecting a second base learner at a final boosting iteration of the plurality of boosting iterations. A processor constructs an ensemble model based on base learners selected and trained during the plurality of boosting iterations.
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公开(公告)号：US11797199B2
公开(公告)日：2023-10-24
申请号：US17368411
申请日：2021-07-06
发明人： Roman Alexander Pletka , Aaron Daniel Fry , Nikolaos Papandreou , Radu Ioan Stoica , Charalampos Pozidis , Nikolas Ioannou
CPC分类号： G06F3/0631 , G06F3/0604 , G06F3/0679 , G06F12/0253 , G06F2212/7205
摘要： A non-volatile memory includes a plurality of physical blocks each including a respective plurality of cells, where each cell is individually capable of storing multiple bits of data. A controller for the non-volatile memory maintains dynamically resizable pools of physical blocks, including at least a low-density pool of physical blocks in which cells are configured to store a fewer number of bits and a high-density pool of physical blocks in which cells are configured to store a greater number of bits. The controller detects an imbalance in utilization between the low-density and high-density pools and, based on detection of the pool imbalance, restricts data placement in the low-density pool, enables garbage collection from the low-density pool back into the low-density pool to compact the low-density pool, and re-enables data placement to the low-density pool based on availability of a threshold number of free physical blocks in the low-density pool.
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公开(公告)号：US20230289061A1
公开(公告)日：2023-09-14
申请号：US17654328
申请日：2022-03-10
发明人： Radu Ioan Stoica , Aaron Daniel Fry , Nikolas Ioannou , Nikolaos Papandreou , Roman Alexander Pletka , Charalampos Pozidis , Jenny L. Brown
IPC分类号： G06F3/06
CPC分类号： G06F3/0611 , G06F3/0655 , G06F3/0679
摘要： A method, system, and computer program product are disclosed. The method includes receiving a write request to a system and calculating, based on operating parameters of the system, a total processing time associated with servicing the write request in the system. The method also includes determining an actual time taken to store data specified in the write request and, when the actual time is less than the total processing time, delaying sending a completion message for the write request to an I/O interface.
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公开(公告)号：US20230177120A1
公开(公告)日：2023-06-08
申请号：US17457698
申请日：2021-12-06
发明人： Nikolaos Papandreou , Charalampos Pozidis , Milos Stanisavljevic , Jan Van Lunteren , Thomas Parnell , Cedric Lichtenau , Andrew M. Sica
CPC分类号： G06K9/6224 , G06K9/6269 , G06N5/003
摘要： A tensor representation of a machine learning inferences to be performed is built by forming complementary tensor subsets that respectively correspond to complementary subsets of one or more leaf nodes of one or more decision trees based on statistics of the one or more leaf nodes of the one or more decision trees and data capturing attributes of one or more split nodes of the one or more decision trees and the one or more leaf nodes of the decision trees. The complementary tensor subsets are ranked such that a first tensor subset and a second tensor subset of the complementary tensor subsets correspond to a first leaf node subset and a second leaf node subset of the complementary subsets of the one or more leaf nodes.
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公开(公告)号：US11567673B1
公开(公告)日：2023-01-31
申请号：US17405672
申请日：2021-08-18
发明人： Radu Ioan Stoica , Nikolas Ioannou , Roman Alexander Pletka , Nikolaos Papandreou , Charalampos Pozidis
摘要： A data storage system includes a plurality of storage devices organized as a redundant array of inexpensive disks (RAID) storage array and a RAID controller. The RAID controller monitors the plurality of storage devices in the RAID storage array. The RAID controller also detects that a host read request of a host has a latency exceeding a latency threshold. Based on the monitoring, the RAID controller determines whether a proactive rebuild of a data requested by the host read request in absence of a data error would likely be beneficial to performance. Based on determining that a proactive rebuild of the data requested by the host read request would likely be beneficial to performance, the RAID controller initiates the proactive rebuild of the data and sends the requested data to the host.
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公开(公告)号：US11264103B2
公开(公告)日：2022-03-01
申请号：US16554371
申请日：2019-08-28
发明人： Nikolaos Papandreou , Charalampos Pozidis , Nikolas Ioannou , Roman Alexander Pletka , Radu Ioan Stoica , Sasa Tomic , Timothy Fisher , Aaron Daniel Fry , Andrew D. Walls
摘要： A computer-implemented method, according to one embodiment, includes: determining a current operating state of a block of memory. The block includes more than one type of page therein, and at least one read voltage is associated with each of the page types. The current operating state of the block is further used to produce a hybrid calibration scheme for the block which identifies a first subset of the read voltages, and a second subset of the read voltages. The read voltages in the second subset are further organized in one or more groupings. A unique read voltage offset value is calculated for each of the read voltages in the first subset, and a common read voltage offset value is also calculated for each grouping of read voltages in the second subset.
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公开(公告)号：US20210334709A1
公开(公告)日：2021-10-28
申请号：US16858900
申请日：2020-04-27
摘要： The present invention is notably directed to a computer-implemented method of training a cognitive model. The cognitive model includes decision trees as base learners. The method is performed using processing means to which a given cache memory is connected, so as to train the cognitive model based on training examples of a training dataset. The cognitive model is trained by running a hybrid tree building algorithm, so as to construct the decision trees and thereby associate the training examples to leaf nodes of the constructed decision trees, respectively. The hybrid tree building algorithm involves a first routine and a second routine. Each routine is designed to access the cache memory upon execution. The first routine involves a breadth-first search tree builder, while the second routine involves a depth-first search tree builder.
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公开(公告)号：US11126360B2
公开(公告)日：2021-09-21
申请号：US16660627
申请日：2019-10-22
摘要： A computer-implemented method, according to one embodiment, is for managing a plurality of blocks of memory in two or more pools. The computer-implemented method includes: maintaining a first subset of the plurality of blocks in a first pool, where the blocks maintained in the first pool are configured in single-level cell (SLC) mode. A second subset of the plurality of blocks is also maintained in a second pool, where the blocks maintained in the second pool are configured in multi-bit-per-cell mode. Current workload input/output (I/O) metrics are also identified during runtime. Moreover, a size of the first subset of blocks in the first pool and a size of the second subset of blocks in the second pool are adjusted based on the current workload I/O metrics.
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公开(公告)号：US11119855B2
公开(公告)日：2021-09-14
申请号：US16663196
申请日：2019-10-24
发明人： Nikolas Ioannou , Timothy Fisher , Roman Alexander Pletka , Nikolaos Papandreou , Radu Ioan Stoica , Sasa Tomic , Aaron Daniel Fry
摘要： A computer-implemented method, according to one embodiment, is for selectively storing parity data in different types of memory which include a higher performance memory and a lower performance memory. The computer-implemented method includes: receiving a write request, and determining whether the write request includes parity data. In response to determining that the write request includes parity data, a determination is made as to whether a write heat of the parity data is in a predetermined range. In response to determining that that write heat of the parity data is in the predetermined range, another determination is made as to whether the parity data has been read since a last time the parity data was updated. Furthermore, in response to determining that the parity data has been read since a last time the parity data was updated, the parity data is stored in the higher performance memory.
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