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公开(公告)号：US09306729B2
公开(公告)日：2016-04-05
申请号：US14154203
申请日：2014-01-14
发明人： Anthony R. Bonaccio , Timothy C. Buchholtz , Rajesh Cheeranthodi , Giri N. Rangan , Sergey V. Rylov
CPC分类号： H04L7/0029 , H03L7/0814 , H04L7/0079 , H04L7/0332 , H04L27/3405
摘要： System, method and computer program product for setting phase control codes to (in-phase) I and (quadrature) Q rotators to a first code pair, different by enough to produce a phase difference between the rotator outputs sufficient to be detected with minimal error by a phase-to-voltage converter. Auxiliary trim DACs are then adjusted according to calibration logic until a comparator output detects a phase difference between the I and Q rotators are within tolerable limits. The resulting trim codes are stored for both the codes in the pair. These trim codes along with the main codes are subsequently applied whenever the codes are used thereafter. These steps are repeated with each successive code pair having the same separation as the first code pair, e.g. both incremented by same amount until all codes have been calibrated. In this manner having the phase separation between all code pairs forced to the same value.
摘要翻译： 将相位控制代码（同相）I和（正交）Q旋转器设置为第一代码对的系统，方法和计算机程序产品，不同于足以产生足够以最小误差检测的旋转器输出之间的相位差 通过一个相电压转换器。 然后根据校准逻辑调整辅助调节DAC，直到比较器输出检测到I和Q旋转器之间的相位差在可容忍的极限内。 对于成对的两个代码，存储所生成的修剪代码。 随后，随着代码的使用，随后应用这些修剪代码以及主要代码。 重复这些步骤，每个连续的代码对具有与第一代码对相同的间隔，例如。 两者都递增相同的量，直到所有代码都被校准。 以这种方式，使所有代码对之间的相位分离强制为相同的值。
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公开(公告)号：US20150294706A1
公开(公告)日：2015-10-15
申请号：US14580589
申请日：2014-12-23
IPC分类号： G11C11/16
CPC分类号： G11C7/065 , G11C7/062 , G11C11/1673 , G11C29/026 , G11C29/028
摘要： Embodiments are directed to a self-reference STT-MRAM sensing scheme that uses offset-cancellation to reduce the impact of FET mismatch and thereby allow the sensing of lower read voltages. In some embodiments, the sensing scheme includes a differential amplifier having a first input connected to a memory cell. In some embodiments, a second input of the differential amplifier may be connected to ground, a common mode voltage of the system or a mid-level supply voltage. The present disclosure provides flexibility with respect to the voltage level at which the sensing is performed (e.g., ground, Voc, Vmid, etc.). The present disclosure provides further flexibility with respect to the sense voltage polarity.
摘要翻译： 实施例涉及使用偏移消除以减少FET失配的影响并因此允许感测较低读取电压的自参考STT-MRAM感测方案。 在一些实施例中，感测方案包括具有连接到存储器单元的第一输入的差分放大器。 在一些实施例中，差分放大器的第二输入可以连接到地，系统的共模电压或中间电源电压。 本公开提供了关于执行感测的电压电平（例如，地面，Voc，Vmid等）的灵活性。 本公开提供了关于感测电压极性的进一步的灵活性。
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公开(公告)号：US08928418B2
公开(公告)日：2015-01-06
申请号：US13766304
申请日：2013-02-13
CPC分类号： G05F3/02 , H03B5/04 , H03B5/1212 , H03B5/1228 , H03B5/1253
摘要： Systems and methods for reducing process sensitivity in integrated circuit (“IC”) fabrication. An integrated circuit structure is provided that includes a first integrated circuit device having at least one parameter influenced by process variation in a first manner. The integrated circuit structure further includes a second integrated device having the least one parameter influenced by the process variation in a second manner. The first manner is opposite of the second manner. The second integrated device is configured to offset or reduce the influence of the process variation on the at least one parameter in the first integrated circuit device.
摘要翻译： 用于降低集成电路（“IC”）制造过程灵敏度的系统和方法。 提供一种集成电路结构，其包括具有以第一方式影响过程变化的至少一个参数的第一集成电路器件。 集成电路结构还包括具有以第二方式受过程变化影响的至少一个参数的第二集成器件。 第一种方式与第二种方式相反。 第二集成装置被配置为抵消或减少处理变化对第一集成电路装置中的至少一个参数的影响。
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公开(公告)号：US08791726B2
公开(公告)日：2014-07-29
申请号：US13733494
申请日：2013-01-03
发明人： Anthony R. Bonaccio , Jingdong Deng , Zhenrong Jin
IPC分类号： H03K3/00
摘要： Recycling energy in a clock distribution network is provided. A circuit includes a clock driver associated with a clock signal and having an output connected to a first load capacitance. The circuit also includes a second load capacitance connected in parallel with the first load capacitance. The circuit further includes a power transfer circuit including an inductor and a transmission gate connected in series between the first load capacitance and the second load capacitance. The power transfer circuit controls a flow of energy between the first load capacitance and the second load capacitance based on the clock signal.
摘要翻译： 提供了时钟分配网络中的回收能量。 电路包括与时钟信号相关联并具有连接到第一负载电容的输出的时钟驱动器。 电路还包括与第一负载电容并联连接的第二负载电容。 电路还包括功率传输电路，其包括串联连接在第一负载电容和第二负载电容之间的电感器和传输栅极。 功率传输电路基于时钟信号控制第一负载电容和第二负载电容之间的能量流动。
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公开(公告)号：US20160182216A1
公开(公告)日：2016-06-23
申请号：US15058625
申请日：2016-03-02
发明人： Anthony R. Bonaccio , Timothy C. Buchholtz , Rajesh Cheeranthodi , Giri N. Rangan , Sergey V. Rylov
CPC分类号： H04L7/0029 , H03L7/0814 , H04L7/0079 , H04L7/0332 , H04L27/3405
摘要： System, method and computer program product for setting phase control codes to (in-phase) I and (quadrature) Q rotators to a first code pair, different by enough to produce a phase difference between the rotator outputs sufficient to be detected with minimal error by a phase-to-voltage converter. Auxiliary trim DACs are then adjusted according to calibration logic until a comparator output detects a phase difference between the I and Q rotators are within tolerable limits. The resulting trim codes are stored for both the codes in the pair. These trim codes along with the main codes are subsequently applied whenever the codes are used thereafter. These steps are repeated with each successive code pair having the same separation as the first code pair, e.g. both incremented by same amount until all codes have been calibrated. In this manner having the phase separation between all code pairs forced to the same value.
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公开(公告)号：US09698968B2
公开(公告)日：2017-07-04
申请号：US15058625
申请日：2016-03-02
发明人： Anthony R. Bonaccio , Timothy C. Buchholtz , Rajesh Cheeranthodi , Giri N. Rangan , Sergey V. Rylov
CPC分类号： H04L7/0029 , H03L7/0814 , H04L7/0079 , H04L7/0332 , H04L27/3405
摘要： System, method and computer program product for setting phase control codes to (in-phase) I and (quadrature) Q rotators to a first code pair, different by enough to produce a phase difference between the rotator outputs sufficient to be detected with minimal error by a phase-to-voltage converter. Auxiliary trim DACs are then adjusted according to calibration logic until a comparator output detects a phase difference between the I and Q rotators are within tolerable limits. The resulting trim codes are stored for both the codes in the pair. These trim codes along with the main codes are subsequently applied whenever the codes are used thereafter. These steps are repeated with each successive code pair having the same separation as the first code pair, e.g. both incremented by same amount until all codes have been calibrated. In this manner having the phase separation between all code pairs forced to the same value.
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公开(公告)号：US20150200765A1
公开(公告)日：2015-07-16
申请号：US14154203
申请日：2014-01-14
发明人： Anthony R. Bonaccio , Timothy C. Buchholtz , Rajesh Cheeranthodi , Giri N. Rangan , Sergey V. Rylov
CPC分类号： H04L7/0029 , H03L7/0814 , H04L7/0079 , H04L7/0332 , H04L27/3405
摘要： System, method and computer program product for setting phase control codes to (in-phase) I and (quadrature) Q rotators to a first code pair, different by enough to produce a phase difference between the rotator outputs sufficient to be detected with minimal error by a phase-to-voltage converter. Auxiliary trim DACs are then adjusted according to calibration logic until a comparator output detects a phase difference between the I and Q rotators are within tolerable limits. The resulting trim codes are stored for both the codes in the pair. These trim codes along with the main codes are subsequently applied whenever the codes are used thereafter. These steps are repeated with each successive code pair having the same separation as the first code pair, e.g. both incremented by same amount until all codes have been calibrated. In this manner having the phase separation between all code pairs forced to the same value.
摘要翻译： 将相位控制代码（同相）I和（正交）Q旋转器设置为第一代码对的系统，方法和计算机程序产品，不同于足以产生足够以最小误差检测的旋转器输出之间的相位差 通过一个相电压转换器。 然后根据校准逻辑调整辅助调节DAC，直到比较器输出检测到I和Q旋转器之间的相位差在可容忍的极限内。 对于成对的两个代码，存储所生成的修剪代码。 随后，随着代码的使用，随后应用这些修剪代码以及主要代码。 重复这些步骤，每个连续的代码对具有与第一代码对相同的间隔，例如。 两者都递增相同的量，直到所有代码都被校准。 以这种方式，使所有代码对之间的相位分离强制为相同的值。
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公开(公告)号：US09252717B2
公开(公告)日：2016-02-02
申请号：US14295794
申请日：2014-06-04
CPC分类号： H03F1/26 , H03B5/10 , H03B5/1212 , H03B5/1225 , H03B5/1228 , H03B5/1243 , H03B5/34 , H03F3/301 , H03F3/45179 , H03F2200/372 , H03F2203/45562 , Y10T29/49119
摘要： An approach for a transconductance cell for use in a voltage controlled oscillator (VCO) is provided. The transconductance cell includes a first NFET stack connected in series to a first PFET stack. The transconductance cell includes a second NFET stack connected in series to a second PFET stack. The first NFET stack and the first PFET stack are cross-coupled to the second NFET stack and the second PFET stack. The first NFET stack and the second NFET stack are connected to a tail node. The first PFET stack and the second PFET stack are connected to a power supply node.
摘要翻译： 提供了一种用于压控振荡器（VCO）的跨导单元的方法。 跨导单元包括与第一PFET堆叠串联连接的第一NFET堆叠。 跨导单元包括与第二PFET堆叠串联连接的第二NFET堆叠。 第一NFET堆叠和第一PFET堆叠交叉耦合到第二NFET堆叠和第二PFET堆叠。 第一个NFET堆叠和第二个NFET堆叠连接到一个尾部节点。 第一PFET堆叠和第二PFET堆叠连接到电源节点。
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