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    CHARGE PUMP CIRCUITS FOR CLOCK AND DATA RECOVERY
    1.
    发明申请
    CHARGE PUMP CIRCUITS FOR CLOCK AND DATA RECOVERY 审中-公开

    公开(公告)号：US20200059348A1

    公开(公告)日：2020-02-20

    申请号：US16664666

    申请日：2019-10-25

    申请人： INPHI CORPORATION

    发明人： Simon FOREY ,  Parmanand MISHRA ,  Michael S. HARWOOD ,  Rajasekhar NAGULAPALLI

    IPC分类号： H04L7/00 ,  H03L7/093 ,  H04L7/033 ,  H03L7/08 ,  H02M3/07

    摘要： The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a charge pump, which can be utilized as a part of a clock data recovery device. Early and late signals are used as differential switching voltage signals in the charge pump. The first switch and a second switch are used for controlling the direction of the current flowing into the loop filter. Input differential voltages to the switches are being generated with an opamp negative feedback loop. The output voltage of the first switch and the second switch is used in conjunction with a resistor to generate a charge pump current. There are other embodiments as well.

    COMPACT HIGH SPEED DUTY CYCLE CORRECTOR
    7.
    发明申请
    COMPACT HIGH SPEED DUTY CYCLE CORRECTOR 审中-公开

    公开(公告)号：US20190044521A1

    公开(公告)日：2019-02-07

    申请号：US16154522

    申请日：2018-10-08

    申请人： INPHI CORPORATION

    发明人： Simon FOREY ,  Rajasekhar NAGULAPALLI ,  Parmanand MISHRA

    IPC分类号： H03L7/08 ,  H04L27/01 ,  H03K5/156 ,  H03G3/20

    CPC分类号： H03L7/0807 ,  H03G3/20 ,  H03K5/1565 ,  H04L27/01

    摘要： Embodiments of the present invention provide techniques for duty cycle correction of clock signals. An input clock signal passes through a pair of output transistors, which provides an output clock signal based on the input clock signal. A duty cycle sensor generates a first correction signal based on the output clock signal. The first correction signal is at least partially opposite of the output clock signal. A duty cycle corrector generates a second correction signal based on the first correction signal. The duty cycle corrector includes two or more transistors for generating the second correction signal. The second correction signal is applied to the output clock signal. There are other embodiments as well.

    COMPACT HIGH SPEED DUTY CYCLE CORRECTOR
    9.
    发明申请
    COMPACT HIGH SPEED DUTY CYCLE CORRECTOR 审中-公开

    公开(公告)号：US20180183444A1

    公开(公告)日：2018-06-28

    申请号：US15840984

    申请日：2017-12-13

    申请人： INPHI CORPORATION

    发明人： Simon FOREY ,  Rajasekhar NAGULAPALLI ,  Parmanand MISHRA

    IPC分类号： H03L7/08 ,  H04L27/01 ,  H03K5/156 ,  H03G3/20

    CPC分类号： H03L7/0807 ,  H03G3/20 ,  H03K5/1565 ,  H04L27/01

    摘要： Embodiments of the present invention provide techniques for duty cycle correction of clock signals. An input clock signal passes through a pair of output transistors, which provides an output clock signal based on the input clock signal. A duty cycle sensor generates a first correction signal based on the output clock signal. The first correction signal is at least partially opposite of the output clock signal. A duty cycle corrector generates a second correction signal based on the first correction signal. The duty cycle corrector includes two or more transistors for generating the second correction signal. The second correction signal is applied to the output clock signal. There are other embodiments as well.