公开(公告)号：US3678469A

公开(公告)日：1972-07-18

申请号：US3678469D

申请日：1970-12-01

Applicant: IBM

Inventor： FREEMAN RICHARD B ,  KAWALEC MICHAEL T ,  MAHOLICK ANDREW W ,  STAGER STANLEY R

IPC: H03M13/09 ,  G08C25/00 ,  G08B29/00 ,  H04L1/10

CPC classification number: H03M13/09

Abstract: Described is a universal cyclic division circuit for developing cyclic redundancy checks upon data wherein the circuitry may be utilized for more than one character size and for more than one polynomial. The system employs a storage device which contains information as to the character size in use as well as storage for the polynomial being used for checking data transmissions over a given communications channel. This information is used to control a universal matrix which uses the stored polynomial to generate the proper cyclic redundancy check character for the new data received and combines it with the cumulative cyclic redundancy check character developed by the matrix for previous characters. Upon the completion of a data transmission, the cyclic redundancy check character developed by the matrix should be identical to the cyclic redundancy check character developed in the transmitter if an error free transmission and reception has occurred.

Abstract translation: 描述了一种通用循环除法电路，用于对数据进行循环冗余校验，其中电路可以用于多于一个字符大小和多于一个多项式。 该系统采用存储装置，该存储装置包含关于使用中的字符尺寸的信息以及用于在给定通信信道上检查数据传输的多项式的存储。 该信息用于控制通用矩阵，该通用矩阵使用存储的多项式为接收到的新数据生成适当的循环冗余校验字符，并将其与由先前字符的矩阵开发的累积循环冗余校验字符组合。 数据传输完成后，如果发生了无错误的发送和接收，则由矩阵开发的循环冗余校验字符应与发送器中开发的循环冗余校验字符相同。