公开(公告)号：US20220374694A1

公开(公告)日：2022-11-24

申请号：US17882360

申请日：2022-08-05

Applicant: Huawei Technologies Co., Ltd. ,  Tsinghua University

Inventor： Bin GAO ,  Qi LIU ,  Leibin NI ,  Kanwen WANG ,  Huaqiang WU

IPC: G06N3/063

Abstract: A neural network circuit is described that includes a first sample-and-hold circuit, a reference voltage generation circuit, a first comparator circuit, and a first output circuit. The first sample-and-hold circuit generates a first analog voltage based on a first output current output by a first neural network computation array. The reference voltage generation circuit generates a reference voltage based on a first control signal. The first comparator circuit is connected to the first sample-and-hold circuit and the reference voltage generation circuit, and outputs a first level signal based on the first analog voltage and the reference voltage. The first output circuit samples the first level signal based on a second control signal, and outputs a first computation result that meets the first computation precision.

公开(公告)号：US20220076746A1

公开(公告)日：2022-03-10

申请号：US17530128

申请日：2021-11-18

Applicant: Huawei Technologies Co., Ltd. ,  TSINGHUA UNIVERSITY

Inventor： Bin GAO ,  Kanwen WANG ,  Junren CHEN ,  Rui ZHANG ,  Huaqiang WU

IPC: G11C13/00 ,  G06N3/063

Abstract: This application provides a storage device and a data writing method. The storage device may be used in a neural network. The storage device includes a memristor unit, a current-controlled circuit, and a write circuit. The memristor unit has a structure of one-transistor and one-resistive random access memory 1T1R. The current-controlled circuit is configured to limit a current passing through the memristor unit to a target current, where the target current is determined based on target conductance of the memristor unit and a gate voltage of the transistor, and the target conductance is used to indicate target data to be written into the memristor unit. The write circuit is configured to load a write voltage to the memristor unit in cooperation with the current-controlled circuit, to write the target data to the memristor unit.

公开(公告)号：US20220277199A1

公开(公告)日：2022-09-01

申请号：US17750052

申请日：2022-05-20

Applicant: Huawei Technologies Co., Ltd. ,  TSINGHUA UNIVERSITY

Inventor： Bin GAO ,  Peng YAO ,  Kanwen WANG ,  Jianxing LIAO ,  Tieying WANG ,  Huaqiang WU

IPC: G06N3/08 ,  G06N3/04

Abstract: A method for data processing in a neural network system and a neural network system are provided. The method includes: inputting training data into a neural network system to obtain first output data, and adjusting, based on a deviation between the first output data and target output data, a weight value stored in at least one in-memory computing unit in some neural network arrays in a plurality of neural network arrays in the neural network system using parallel acceleration. The some neural network arrays are configured to implement computing of some neural network layers in the neural network system. The method may improve performance and recognition accuracy of the neural network system.

公开(公告)号：US20220327242A1

公开(公告)日：2022-10-13

申请号：US17847843

申请日：2022-06-23

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Bin GAO

IPC: G06F21/64 ,  G06F21/62

Abstract: A data management apparatus determines an association relationship between first service data and first authorization information based on an association relationship between a first source file and the first authorization information, where the first service data is data obtained based on the first source file; and the data management apparatus manages the first service data based on the first authorization information. At least one embodiment is applied to a legal and compliant use scenario of service data after the service data is authorized, and are used to quickly and accurately trace information such as a use scope, a validity period, and a user of the service data. Based on this technology, unauthorized use is effectively limited.

公开(公告)号：US20230244919A1

公开(公告)日：2023-08-03

申请号：US18097651

申请日：2023-01-17

Applicant: TSINGHUA UNIVERSITY

Inventor： Huaqiang WU ,  Xiangpeng LIANG ,  Ya?nan ZHONG ,  Jianshi TANG ,  Bin GAO ,  He QIAN

IPC: G06N3/063

CPC classification number: G06N3/063

Abstract: At least one embodiment of the present disclosure provides a reservoir computing apparatus and a data processing method. The reservoir computing apparatus includes: a signal input circuit, configured to receive an input signal; a reservoir circuit, including a plurality of reservoir sub-circuits, in which each reservoir sub-circuit includes a mask sub-circuit and a rotating neuron sub-circuit, the mask sub-circuit is configured to perform a first processing on the input signal with a first weight to obtain a first processing result, and the rotating neuron sub-circuit is configured to perform a second processing on the first processing result to obtain a second processing result; and an output layer circuit, configured to multiply a plurality of second processing results by a second weight matrix to obtain a third processing result. The reservoir computing apparatus optimizes operation efficiency and reduces implementation costs.

公开(公告)号：US20250095728A1

公开(公告)日：2025-03-20

申请号：US18580872

申请日：2021-12-13

Applicant: TSINGHUA UNIVERSITY

Inventor： Bin GAO ,  Peng YAO ,  Huaqiang WU ,  Jianshi TANG ,  He QIAN

IPC: G11C13/00

Abstract: A computing apparatus and a robustness processing method thereof. The robustness processing method includes: based on model parameters of a target algorithm model, obtaining a mapping relationship between the model parameters and the first computing memristor array; based on an influence factor that determines a critical weight device, determining a way to obtain a weight criticality of the plurality of memristor devices from the influence factor; obtaining an input set of the algorithm model, and determining a criticality value for each of the plurality of memristor devices according to the way; determining a critical weight device among the plurality of memristor devices according to the criticality value for each of the plurality of memristor devices; and based on the critical weight device, performing an optimization processing on the first processing unit.

公开(公告)号：US20220277866A1

公开(公告)日：2022-09-01

申请号：US17747906

申请日：2022-05-18

Applicant: Tsinghua University ,  Tencent Technology (Shenzhen) Company Limited

Inventor： Jianshi TANG ,  Zhenxuan ZHAO ,  Yuan DAI ,  Wangwei LEE ,  Zhengyou ZHANG ,  Jian YUAN ,  Huaqiang WU ,  He QIAN ,  Bin GAO

IPC: H01B1/24 ,  C08K3/04 ,  C09D5/24 ,  C09D7/61 ,  C09D7/40 ,  C09D175/04

Abstract: This application discloses a conductive paste, a preparation method thereof, and a preparation method of a conductive film using the conductive paste. The conductive paste comprises: a thermoplastic polyurethane, conductive particles, and an organic solvent, the thermoplastic polyurethane and the conductive particles being proportionally mixed in the organic solvent, and the thermoplastic polyurethane being dispersed in the form of particles among the conductive particles. A thermoplastic polyurethane elastomer is used as a binder, and the conductive particles are mixed in the organic solvent containing the thermoplastic polyurethane elastomer. The conductive particles ensure the conductivity of the conductive film prepared using the conductive paste. The thermoplastic polyurethane has strong adhesion ability, and is suitable for use on the surface of most substrates, to form a conductive film with good adhesion and no cracking.

公开(公告)号：US20220137941A1

公开(公告)日：2022-05-05

申请号：US17517096

申请日：2021-11-02

Applicant: TSINGHUA UNIVERSITY

Inventor： Huaqiang WU ,  Ruihua YU ,  Yilong GUO ,  Jianshi TANG ,  Bin GAO ,  He QIAN

IPC: G06F8/41 ,  G06N3/10 ,  G06F17/16

Abstract: A compilation method, a compilation apparatus suitable for an In-Memory Computing apparatus, a computing device and a storage medium. The compilation method includes: acquiring calculation information of an algorithm to be compiled; converting the algorithm to be compiled into the first intermediate representation according to the calculation information; mapping the first intermediate representation to the second intermediate representation; and compiling the algorithm to be compiled into instruction information recognized by the In-Memory Computing apparatus according to the hardware information, to make the In-Memory Computing apparatus execute the instruction information. The compilation method may compile the calculation information into instructions that may be directly executed by the In-Memory Computing apparatus, so as to realize the effect of accelerating the operations of various algorithms by using the In-Memory Computing apparatus.

公开(公告)号：US20250078924A1

公开(公告)日：2025-03-06

申请号：US18726931

申请日：2022-01-11

Applicant: TSINGHUA UNIVERSITY

Inventor： Huaqiang WU ,  Zhengwu LIU ,  Han ZHAO ,  Jianshi TANG ,  Bin GAO ,  He QIAN

IPC: G11C13/00 ,  G06F17/16

Abstract: At least one embodiment of the present disclosure provides a data processing method based on a memristor array and an electronic apparatus. The data processing method includes: acquiring a plurality of first analog signals; setting the memristor array, and writing data of a parameter matrix corresponding to the data processing into the memristor array; and inputting the plurality of first analog signals into a plurality of column signal input terminals of the set memristor array, respectively, controlling operation of the memristor array to perform the data processing on the plurality of first analog signals, and obtaining a plurality of second analog signals after performing the data processing at a plurality of row signal output terminals of the memristor array, respectively.

公开(公告)号：US20230004357A1

公开(公告)日：2023-01-05

申请号：US17779834

申请日：2020-11-13

Applicant: TSINGHUA UNIVERSITY

Inventor： Huaqiang WU ,  Bohan LIN ,  Bin GAO ,  Jianshi TANG ,  He QIAN

IPC: G06F7/58

Abstract: A method for generating a random number and a random number generator are provided. The method for generating a random number includes: performing n writing operations on at least one analog resistive random access memory, where each of the n writing operations includes applying at least one writing operation pulse to change a conductance value of an operated analog resistive access memory; and generating the random number based on n writing operation pulse numbers respectively corresponding to the n writing operations, where n is a positive integer. The method for generating a random number generates random numbers based on the analog characteristics of the analog resistive random access memory, the generated random number does not need back-end correction, and have both high speed and high reliability.