DEVICE AND METHOD FOR DISPLAYING A 3D IMAGE

    公开(公告)号:US20210120228A1

    公开(公告)日:2021-04-22

    申请号:US17136958

    申请日:2020-12-29

    Abstract: The invention relates to the technical field of Multifocal Plane Display (MFD) devices for displaying 3D images. In particular, the invention proposes a device for displaying a 3D image, wherein the 3D image is generated based on a 2D image and a depth map. The device includes a light source, a diffuser and a controller. The light source is configured to emit light beams, each light beam corresponding to a pixel of a 2D image. The diffuser is configured to diffuse the light beams, wherein the diffuser includes a plurality of diffuser elements distributed across a 3D volume, and each diffuser element is individually controllable to be transmissive or diffusive. The controller is configured to control each diffuser element to be transmissive or diffusive based on a depth map.

    SYNCHRONIZATION METHOD AND DEVICE

    公开(公告)号:US20220248353A1

    公开(公告)日:2022-08-04

    申请号:US17725962

    申请日:2022-04-21

    Abstract: Embodiments of this application disclose a synchronization method and a device. First, a device marks, based on a preset period, a periodic code block in a data bitstream to be sent from a MAC layer to a PHY layer, then sends the data bitstream to a peer device through the PHY layer, records a sending time of each periodic code block as a first timestamp during sending, and returns the first timestamp to the MAC layer. To be specific, by marking a timestamp for the periodic code block received from the MAC layer, the device sets a PHY-layer-based time reference scale (namely, the first timestamp) at the PHY layer.

    SYSTEM, APPARATUS AND METHOD FOR DISPLAYING IMAGE DATA

    公开(公告)号:US20200053327A1

    公开(公告)日:2020-02-13

    申请号:US16659255

    申请日:2019-10-21

    Abstract: The present invention provides a display system 100 for displaying image data. The display system 100 comprises a light source 101; a spatial light modulator 102 including a plurality of controllable reflective elements 1020; a light source controller 103, configured to control the light source 101 to emit, in each of a plurality of time intervals, light with a different illumination power level, wherein the time intervals have the same length; and a spatial light modulator controller 104, configured to activate, based on received image data, the plurality of controllable elements for at least one of the time intervals for directing the light from the light source for display the image data. Accordingly, the frame rate and bandwidth of the display system 100 are increased significantly so as to be suitable for the light filed applications.

    DATA SENDING METHOD AND APPARATUS, AND FLEXE SWITCHING SYSTEM

    公开(公告)号:US20210250112A1

    公开(公告)日:2021-08-12

    申请号:US17242929

    申请日:2021-04-28

    Abstract: This application discloses a data sending method and apparatus, and a FlexE switching system. When slice packets received by a sending module include a SOP flag and a EOP flag of a same data packet, it indicates that the sending module receives a complete data packet, and immediately sends data packet slices, or sends the data packet slices after a latency of first preset duration. In this way, a stream inside the data packet is not interrupted, a data sending latency is reduced, and transmission efficiency is improved. When the slice packets received by the sending module include a SOP flag of a data packet but do not include a EOP flag of the data packet, it indicates that the sending module has not received a complete data packet, and then sends data packet slices after a latency of second preset duration longer than the first preset duration.

    DYNAMIC LINK ADJUSTMENT METHOD AND LINK MANAGING DEVICE
    7.
    发明申请
    DYNAMIC LINK ADJUSTMENT METHOD AND LINK MANAGING DEVICE 有权
    动态链路调整方法和链路管理设备

    公开(公告)号:US20140044138A1

    公开(公告)日:2014-02-13

    申请号:US13961423

    申请日:2013-08-07

    CPC classification number: H04J3/0605 H04L7/10 H04L25/14

    Abstract: A receiving-side chip is disclosed according to the present invention, which includes a processor, configured to acquire and execute following instructions: receiving link information sent by a sending-side chip, and enabling, according to the link information, a SerDes link to be added; receiving padding data from the added SerDes link according to a short unit frame period to acquire a synchronization word, and determining, according to the synchronization word, whether the added SerDes link has been synchronized; switching a read period of data in the added SerDes link from the short unit frame period into a long unit frame period, and aligning the data of the added SerDes link with the data of an original SerDes link; and receiving service data over the added SerDes link and the original SerDes link.

    Abstract translation: 根据本发明公开了一种根据本发明的接收侧芯片,其包括:处理器,被配置为获取和执行以下指令:接收由发送侧芯片发送的链路信息,并且根据链路信息使得能够将SerDes链路 被添加 根据短单位帧周期从所添加的SerDes链路接收填充数据以获取同步字,并根据所述同步字确定添加的SerDes链路是否已被同步; 将添加的SerDes链路中的数据的读取周期从短单位帧周期切换到长单位帧周期,并且将所添加的SerDes链路的数据与原始SerDes链路的数据对齐; 并通过添加的SerDes链接和原始SerDes链接接收服务数据。

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