TIME-TO-DIGITAL CONVERTER AND DIGITAL PHASE LOCKED LOOP

    公开(公告)号:US20190173477A1

    公开(公告)日:2019-06-06

    申请号:US16256477

    申请日:2019-01-24

    Abstract: A time-to-digital converter includes N stages of converting circuits, where N2, and N is an integer. Each stage of the converting circuit includes a first delayer and an arbiter; an output end of the first delayer in each stage of the converting circuit outputs a delayed signal of the stage of the converting circuit; and the arbiter in each stage of the converting circuit receives a sampling clock and the delayed signal of the stage of the converting circuit, and compares the sampling clock with the delayed signal to obtain an output signal of the stage of the converting circuit. The first delayer in each stage of the converting circuit includes at least one first delay cell circuit with a first time unit. The first delayer in any stage of the converting circuit includes a less number of first delay cell circuits than the first delayer in a next stage of the converting circuit.

    COMMUNICATION METHOD AND RELATED DEVICE

    公开(公告)号:US20210013939A1

    公开(公告)日:2021-01-14

    申请号:US17039345

    申请日:2020-09-30

    Abstract: Embodiments of this application provide a communication method and a related device. The method is applied to a base station. The base station includes a plurality of antenna arrays and a baseband processing unit. The plurality of antenna arrays are distributed around a communication area and are all connected to the baseband processing unit. A terminal in the communication area is configured to perform signal transmission with the antenna arrays, to implement communication with the baseband processing unit. The method includes: when an obstacle exists between the terminal and a primary antenna array performing signal transmission with the terminal, controlling, by the base station through the baseband processing unit, a secondary antenna array to perform signal transmission with the terminal, where the primary antenna array and the secondary antenna array are in the antenna arrays included in the base station, and in the plurality of antenna arrays except the primary antenna array, the secondary antenna array is an antenna array with highest quality of signals between the antenna array and the terminal. According to the embodiments of this application, smooth communication between the terminal and the base station can be ensured.

    TIME-TO-DIGITAL CONVERTER AND DIGITAL PHASE LOCKED LOOP

    公开(公告)号:US20170373698A1

    公开(公告)日:2017-12-28

    申请号:US15685447

    申请日:2017-08-24

    CPC classification number: H03M1/002 G04F10/005 H03L7/0814 H03M1/502

    Abstract: A time-to-digital converter including N stages of converting circuits, where N≧2, and N is an integer. Each stage of converting circuit includes a first delayer and an arbiter; an output end of the first delayer in each stage of converting circuit outputs a delayed signal of the stage of converting circuit; and the arbiter in each stage of converting circuit receives a sampling clock and the delayed signal of the stage of converting circuit, and compares the sampling clock with the delayed signal to obtain an output signal of the stage of converting circuit. Output signals of the N stages of converting circuits form a non-linear binary number, to indicate a time difference between a clock signal and a reference signal.

Patent Agency Ranking