公开(公告)号：US20170272385A1

公开(公告)日：2017-09-21

申请号：US15461666

申请日：2017-03-17

Applicant: Huawei Technologies Co., Ltd.

Inventor： Hengchao Xin ,  Han Lin ,  Jing Xia

IPC: H04L12/935 ,  H04L12/26

CPC classification number: H04L49/30 ,  H04L43/08 ,  H04L49/109

Abstract: A chip is provided, where the chip is formed by packaging at least two dies, and the at least two dies form at least one die group. The die group includes a first die and a second die. A first processing unit and n groups of ports are disposed on the first die, and a second processing unit and m groups of ports are disposed on the second die. The first processing unit is configured to: switch at least one group of first type ports in the n groups of ports from input to output and switch a second type port that is in the m groups of ports and that is coupled to each group of the first type ports from output to input.

公开(公告)号：US20240281381A1

公开(公告)日：2024-08-22

申请号：US18592356

申请日：2024-02-29

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Han Lin ,  Yuxuan Chen ,  JIANJIANG ZENG

IPC: G06F12/10 ,  G06F12/0815

CPC classification number: G06F12/10 ,  G06F12/0815

Abstract: This application discloses a data storage apparatus and a data processing method. The data storage apparatus includes a memory and a first near-data processing NDP unit, the first NDP unit is electrically connected to the memory, and the data storage apparatus is connected to a processor through a bus. The first NDP unit is configured to store first physical address information. The information points to first address space, and the first address space is a section of contiguous memory space that the first NDP unit has permission to use. The memory is configured to store, in the first address space, first data from the processor. The first NDP unit is further configured to read a part or all of the first data from the first address space based on an obtained first offset address and the first physical address information, and perform computation.

公开(公告)号：US10135758B2

公开(公告)日：2018-11-20

申请号：US15461666

申请日：2017-03-17

Applicant: Huawei Technologies Co., Ltd.

Inventor： Hengchao Xin ,  Han Lin ,  Jing Xia

IPC: H04L12/935 ,  H04L12/26 ,  H04L12/933

Abstract: A chip is provided, where the chip is formed by packaging at least two dies, and the at least two dies form at least one die group. The die group includes a first die and a second die. A first processing unit and n groups of ports are disposed on the first die, and a second processing unit and m groups of ports are disposed on the second die. The first processing unit is configured to: switch at least one group of first type ports in the n groups of ports from input to output and switch a second type port that is in the m groups of ports and that is coupled to each group of the first type ports from output to input.